Electrically programmable resistance cross point memory structure
View Patent ↗Resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises an active layer of perovskite material interposed between upper electrodes and lower electrodes. A bit region located within the active layer at the cross point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. Memory circuits are provided to aid in the programming and read out of the bit region.
1. A memory structure comprising;
a) a substrate;
b) a plurality of bottom electrodes overlying the substrate;
c) a plurality of top electrodes overlying the bottom electrodes; and
d) a continuous active layer interposed between the plurality of top electrodes and the plurality of bottom electrodes, wherein the continuous active layer is a perovskite material.
2. The memory structure of claim 1 , wherein the bottom electrodes comprise a bottom electrode material that allows for epitaxial formation of the continuous active layer overlying the bottom electrodes.
3. The memory structure of claim 2 , wherein the bottom electrode material is YBCO.
4. The memory structure of claim 1 , wherein the bottom electrode material is platinum.
5. The memory structure of claim 1 , wherein the continuous active layer is a colossal magnetoresistance (CMR) material.
6. The memory structure of claim 1 , wherein the continuous active layer is Pr 0.7 Ca 0.3 MnO 8 (PCMO).
7. The memory structure of claim 1 , wherein the continuous active layer is Gd 0.7 Ca 0.3 BaCo 2 O 5+5 .
8. The memory structure of claim 1 , wherein the substrate comprises an amorphous material, a polycrystalline material or a crystalline material.
9. The memory structure of claim 8 , wherein the substrate comprises Si, LaAlO 3 , or TiN.
10. The memory structure of claim 1 , wherein the plurality of bottom electrodes comprise substantially parallel rows.
11. The memory structure of claim 1 , wherein the plurality of top electrodes comprise substantially parallel lows.
12. The memory structure of claim 1 , wherein the plurality of bottom electrodes and the plurality of top electrodes overlying the plurality of bottom electrodes form a cross point array.
13. The memory structure of claim 12 , wherein the plurality of top electrodes overlie the plurality of bottom electrodes at a substantially ninety degree angle.
14. The memory structure of claim 1 , wherein the plurality of bottom electrodes is between about 5 nm and 500 nm thick.
15. The memory structure of claim 1 , wherein the continuous active layer is between about 5 nm and 600 nm thick.
16. The memory structure of claim 1 , wherein the plurality of top electrodes comprise platinum, copper, silver, or gold.
17. A memory structure comprising;
a) a substrate;
b) a plurality of bottom electrodes overlying the substrate, wherein the plurality of bottom electrodes comprise substantially parallel rows;
c) a plurality of top electrodes, which comprise substantially parallel rows, overlying the bottom electrodes at a substantially ninety degree angle, whereby a cross point is formed at each point where one of the plurality of top electrodes crosses over one of the plurality of bottom electrodes; and
d) a continuous active layer interposed between the plurality of top electrodes and the plurality of bottom electrodes and extending through more than one cross point.
18. The memory structure of claim 17 , wherein the continuous active layer is Pr 0.7 Ca 0.3 MnO 3 (PCMO).
19. The memory structure of claim 17 , wherein the continuous active layer is Gd 0.7 Ca 0.3 BaCo 2 O 5+5 .