Reduced gate delay multiplexed interface and output buffer circuit for integrated circuit devices incorporating random access memory arrays
View Patent ↗A reduced gate delay multiplexed interface and output buffer circuit for random access memory arrays, such as synchronous dynamic random access memory (“SDRAM”) devices, or other integrated circuit devices incorporating embedded memory arrays which reduces data access time and clock latency. In accordance with the present invention, data is multiplexed (or selected) and driven out at the memory bank level rather than at the output pad area (or the embedded RAM macro edge) as in prior art techniques.
1. An integrated circuit device comprising:
a memory array including a plurality of memory banks
a plurality of sub-array interface circuits coupled to complementary data read local lines of said device, each receiving a read enable signal, and each further coupled to complementary data read lines; and
a plurality of interface and output buffer circuits, wherein each of said plurality of memory banks includes a respective bank interface and output buffer circuit, and wherein each of said plurality of interface and output buffer circuits is coupled to a data output line of said device and receives a main sense amplifier enable signal to provide a data output signal,
wherein there are no additional clocked stages between a sub-array interface circuit and a corresponding interface and output buffer circuit.
2. The integrated circuit device of claim 1 wherein said interface and output buffer circuit comprises:
a main sense amplifier coupled to complementary data read lines and a main sense amplifier enable signal to provide a data output signal.
3. The integrated circuit device of claim 2 wherein said interface and output buffer circuit further comprises:
an output stage coupled to receive said data output signal, said data output stage receiving at least one main sense amplifier delay signal and operative to selectively couple said data output signal to said data output line in response to said main sense amplifier delay signal.
4. The integrated circuit device of claim 3 wherein said output stage further comprises:
first and second pass gates coupled to receive said data output signal and operative in response to complementary ones of said at least one main sense amplifier delay signal to couple said data output signal to said data output line.
5. The integrated circuit device of claim 4 wherein said first and second pass gates comprise CMOS transmission gates.
6. The integrated circuit device of claim 4 wherein said output stage further comprises:
first and second output switching devices defining an output node coupled to said data output line, said first output switching device having a control terminal thereof coupled to an output of said first pass gate and said second output switching device having a control terminal thereof coupled to an output of said second pass gate.
7. The integrated circuit device of claim 6 wherein said first and second output switching devices comprise MOS transistors.
8. The integrated circuit device of claim 7 wherein said first output switching device is a P-channel device and said second output switching device is an N-channel device.
9. The integrated circuit device of claim 6 further comprising:
a pull-up device for selectively coupling said output of said first pass gate to a supply voltage source in response to a first state of said main sense amplifier delay signal; and
a pull-down device for selectively coupling said output of said second pass gate to a reference voltage source in response to a second opposite state of said main sense amplifier delay signal.
10. The integrated circuit device of claim 9 wherein said pull-up and pull-down devices comprise MOS transistors.
11. The integrated circuit device of claim 10 wherein said pull-up device comprises a P-channel device and said pull-down device comprises an N-channel device.
12. The integrated circuit device of claim 1 wherein
an interface and output buffer circuit of the plurality of interface and output buffer circuits is associated with each of said plurality of memory banks, said interface and output buffer circuit comprising a main sense amplifier circuit operative in response to an enable signal and an output stage coupled to said main sense amplifier circuit and a data output line of said device and operative in response to a delayed enable signal.
13. The integrated circuit device of claim 12 wherein said main sense amplifier is coupled to said complementary data read lines and said enable signal to provide a data output signal.
14. The integrated circuit device of claim 13 wherein said output stage is coupled to receive said data output signal and is operative to selectively couple said data output signal to said data output line in response to said delayed enable signal.
15. The integrated circuit device of claim 14 wherein said output stage further comprises:
first and second pass gates coupled to receive said data output signal and operative in response to said delayed enable signal to couple said data output signal to said data output line.
16. The integrated circuit device of claim 15 wherein said first and second pass gates comprise CMOS transmission gates.
17. The integrated circuit device of claim 15 wherein said output stage further comprises:
first and second output switching devices defining an output node coupled to said data output line, said first output switching device having a control terminal thereof coupled to an output of said first pass gate and said second output switching device having a control terminal thereof coupled to an output of said second pass gate.
18. The integrated circuit device of claim 17 wherein said first and second output switching devices comprise MOS transistors.
19. The integrated circuit device of claim 18 wherein said first output switching device is a P-channel device and said second output switching device is an N-channel device.
20. The integrated circuit device of claim 16 further comprising:
a pull-up device for selectively coupling said output of said first pass gate to a supply voltage source in response to a first state of said delayed enable signal; and
a pull-down device for selectively coupling said output of said second pass gate to a reference voltage source in response to a second opposite state of said delayed enable signal.
21. The integrated circuit device of claim 20 wherein said pull-up and pull-down devices comprise MOS transistors.
22. The integrated circuit device of claim 21 wherein said pull-up device comprises a P-channel device and said pull-down device comprises an N-channel device.