Frequency agile tuner and variable rate decimator for digital demodulator

1. An apparatus for demodulating a digital input signal having a pre-assigned symbol rate by using a single sample clock signal; said pre-assigned symbol rate is selected from the group consisting of a plurality of symbol rates; said apparatus comprising:

a Complex Mixer configured to down convert an input digital signal having said pre-assigned symbol rate signal from a carrier frequency to a baseband frequency;

a Cascaded Integrated Comb (CIC) Decimator filter electrically communicating with said Complex Mixer, said CIC Decimator configured to perform a filtering-decimation operation to isolate a down converted digital signal having a pre-assigned symbol rate, and configured to output an Inphase (I) component and a Quadrature (Q) component of a CIC_output_signal having a CIC-shaped decimated spectrum;

a Shaper filter electrically communicating with said (CIC) Decimator filter, said Shaper filter is configured to restore an original spectrum of said I and Q components of said CIC_output_signal having said CIC-shaped decimated spectrum; said Shaper filter configured to output I and Q components of a shaper_filter_output_signal, wherein said I component and said Q component of said shaper_filter_output_signal include a shaper_signal component having a restored original spectrum of said pre-assigned signal and include an adjacent shaper-signal component having a spectrum that is adjacent to said restored original spectrum of said pre-assigned signal;

a CIC cutoff filter electrically communicating with said Shaper filter; said CIC cutoff filter configured to pass said shaper_signal component having said restored original spectrum of said pre-assigned signal; said CIC cutoff filter configured to pass a part of said adjacent signal having a spectrum part that is carved out by a frequency response function of said CIC cutoff filter;

a Demodulator electrically communicating with said CIC cutoff filter; said Demodulator configured to demodulate and to extract a frequency component from said shaper_signal component having said restored original spectrum of said pre-assigned signal;

a Coarse Frequency estimation block electrically communicating with said Demodulator; said Coarse Frequency estimation block configured to estimate a frequency offset between said pre-assigned carrier frequency and said frequency component of said shaper_signal component having said restored original spectrum of said pre-assigned signal;

and

a CIC tuner loop filter electrically communicating with said Coarse Frequency estimation block; said CIC tuner loop filter configured to insert said estimated by said Coarse Frequency estimation block frequency offset into a carrier loop in order to complete a carrier recovery of said pre-assigned input digital signal.

2. The apparatus of claim 1 , wherein said CIC Decimator further includes:

a programmable CIC Decimator having a CIC_Decimator_programmable frequency response function.

3. The apparatus of claim 2 , wherein said Shaper filter further includes:

a programmable Shaper filter having a Shaper_filter_programmable frequency response function.

4. The apparatus of claim 3 , wherein said Shaper_filter_programmable frequency response function is equal to an inverse function of said CIC_Decimator_programmable frequency response function within a Bandwidth (BW) of said pre-assigned input digital signal.

5. The apparatus of claim 3 , wherein said Shaper filter further includes:

a Finite Impulse Response (FIR) filter including an integer L taps.

6. The apparatus of claim 3 , wherein said Shaper filter further includes:

a Finite Impulse Response (FIR) filter including an integer L of taps and including an integer L of filter coefficients; wherein said FIR filter includes a frequency response function depending on said integer L.

7. The apparatus of claim 1 , wherein said CIC Decimator further includes:

a plurality of CIC integrators;

and

a plurality of Comb filters.

8. The apparatus of claim 1 , wherein said CIC Decimator further includes:

an integer K-stage integrator further including:

an integer K of parallel CIC integrators;

an integer K of Numerical Control Oscillators (NCO) s;

and

an integer K of CIC mixers;

wherein said K-stage integrator is configured to increase by a K-factor a processing speed of said incoming digital input signal having said pre-assigned data rate.

9. The apparatus of claim 8 , wherein said CIC Decimator further includes:

at least one Comb filter further including:

an integer M-section cascaded comb filter; and wherein each said section of said M-section cascaded comb filter further includes:

an integer N of registers;

and

a substracter;

and

a decimation block;

and wherein each said section of said M-section cascaded comb filter having said integer N of registers differentiates said decimated integrated output of said K-stage integrator with a combinatorial delay of N samples;

and wherein said decimation block decimates an output signal of said M-section cascaded comb filter by a decimation factor R;

and wherein said CIC Decimator requires log 2 [(RN)] M additional bits as compared with a number of bits in said input digital data signal to avoid overflow; wherein R is an integer.

10. The apparatus of claim 9 , wherein said integer M of sections in said M-section cascaded comb filter is equal to said integer K of stages in said K-stage integrator.

11. The apparatus of claim 9 further including:

a plurality of pipeline registers, each said pipeline register being located between at least two consecutive sections of said M-section cascaded comb filter;

wherein each said pipeline register is configured to perform a pipeline computation on a plurality of input symbols in order to increase the speed of operation of each said section of said M-section cascaded comb filter by N-factor by minimizing said combinatorial delay of N samples;

and wherein a pipeline delay of said CIC Decimator having said plurality of pipeline registers is determined by one said section of said M-section cascaded comb filter; each said section of said M-section cascaded comb filter having said integer N registers.

12. The apparatus of claim 9 further including:

an integer M of pipeline registers, each said pipeline register being located within one said section of said M-section cascaded comb filter;

and wherein each said pipeline register is used as said substracter in one said section of said M-section cascaded comb filter;

and wherein each said pipeline register is configured to perform a pipeline computation on a plurality of input symbols in order to increase the speed of operation of each said section of said M-section cascaded comb filter by said M-factor;

and wherein a single section delay caused by said M-section cascaded comb filter is determined by one said section having said integer N registers.

13. The apparatus of claim 8 , wherein said CIC Decimator further includes:

said integer K of parallel CIC integrators;

and

a plurality of pipeline registers; each said pipeline register being used as one said CIC mixer;

and wherein each said pipeline register is configured to perform a pipeline computation on a plurality of input symbols in order to increase the speed of operation of each said CIC integrator by said K-factor.

14. The apparatus of claim 1 , wherein said CIC tuner loop filter further includes:

an adaptive CIC tuner loop configured to perform an adaptive carrier loop frequency adjustment to compensate for a change in an external parameter selected from the group consisting of: {temperature; humidity; and at least one circuit elements aging parameter}.

15. The apparatus of claim 14 , wherein said adaptive CIC tuner loop further includes:

a controller configured to generate a control update signal;

a nominal frequency update block electrically communicating with said controller and configured to update a nominal frequency coefficient in said adaptive CIC tuner loop using said control update signal;

a coarse frequency offset update block electrically communicating with said controller and configured to update a coarse frequency offset coefficient in said adaptive CIC tuner loop using said control update signal;

and

a phase update block electrically communicating with said controller and configured to update a phase coefficient in said adaptive CIC tuner loop using said control update signal.

16. The apparatus of claim 15 , wherein said adaptive CIC tuner loop further includes:

a frequency accumulator, and a phase accumulator;

and wherein said controller further includes:

an algorithm comprising at least the following steps:

if a frequency update in said frequency accumulator exceeds a predetermined high frequency threshold; use a plurality of negative frequency coefficients for a next loop frequency update;

if said frequency update in said frequency accumulator is lower than a predetermined low frequency threshold; use a plurality of positive frequency coefficients for said next loop frequency update;

if a phase update in said phase accumulator exceeds a predetermined high phase threshold; use a plurality of negative phase coefficients for a next loop phase update;

and

if said phase update in said phase accumulator is lower than a predetermined low phase threshold; use a plurality of positive phase coefficients for said next phase loop update.

17. A method for demodulating a digital input signal having a pre-assigned symbol rate by using a single sample clock signal; said pre-assigned symbol rate is selected from the group consisting of a plurality of symbol rates; said method comprising the steps of:

down converting an input digital signal having said pre-assigned symbol rate from a carrier frequency to a baseband frequency by using a Complex Mixer;

performing a filtering-decimation operation by using a Cascaded Integrated Comb (CIC) Decimator filter in order to isolate a down converted digital signal having said pre-assigned symbol rate;

generating a CIC_output_signal having a CIC-shaped decimated spectrum by using said (CIC) Decimator filter;

restoring an original spectrum of said CIC_output_signal having said CIC-shaped decimated spectrum by using a Shaper filter, wherein an I component and Q component of a shaper_filter_output_signal include a shaper_signal component having said restored original spectrum of said pre-assigned signal and include an adjacent shaper-signal component having a spectrum that is adjacent to said restored original spectrum of said pre-assigned signal;

using a CIC cutoff filter to pass said shaper_signal component having a restored original spectrum of said pre-assigned signal and to pass a part of said adjacent signal having a spectrum part that is carved out by a frequency response function of said CIC cutoff filter;

demodulating and extracting a frequency component from said shaper_signal component having said restored original spectrum of said pre-assigned signal by using a Demodulator;

estimating a frequency offset between said pre-assigned carrier frequency and said frequency component of said shaper_signal component having said restored original spectrum of said pre-assigned signal by using a Coarse Frequency estimation block;

and

completing a carrier recovery of said pre-assigned input digital signal by inserting said estimated by said Coarse Frequency estimation block frequency offset into a carrier loop by using a CIC tuner loop filter.

18. The method of claim 17 further including the step of:

programming a frequency response function of said CIC Decimator.

19. The method of claim 17 further including the step of:

programming a frequency response function of said Shaper filter, wherein said Shaper_filter_programmable frequency response function is equal to an inverse function of said CIC_Decimator_programmable frequency response function within a Bandwidth (BW) of said pre-assigned input digital signal.

20. The method of claim 17 , said CIC Decimator further including at least one Comb filter further including an integer M-section cascaded comb filter and decimation block, each said section of said M-section cascaded comb filter further including an integer N of registers, and a substracter, and wherein said decimation block decimates an output signal of said M-section cascaded comb filter by a decimation factor R; said method further including the step of:

performing a pipeline computation on a plurality of input symbols in order to increase the speed of operation of each said section of said M-section cascaded comb filter by N-factor by minimizing said combinatorial delay of N samples; wherein a pipeline delay of said CIC Decimator having said plurality of pipeline registers is determined by one said section of said M-section cascaded comb filter.

21. The method of claim 17 , said CIC tuner loop filter further including an adaptive CIC tuner loop, said method further including the step of:

performing an adaptive carrier loop frequency adjustment to compensate for a change in an external parameter selected from the group consisting of: {temperature; humidity; and at least one circuit elements aging parameter}.

22. The method of claim 21 , wherein said step of performing said adaptive carrier loop frequency adjustment further includes the steps of:

generating a control update signal by using a controller;

updating a nominal frequency coefficient in said adaptive CIC tuner loop by using a nominal frequency update block under control of said control update signal;

updating a coarse frequency offset coefficient in said adaptive CIC tuner loop by using a coarse frequency offset update block under control of said control update signal;

and

updating a phase coefficient in said adaptive CIC tuner loop by using a phase update block under control of said control update signal.

23. The method of claim 17 further including the step of:

selecting a passband mode or a baseband mode of operation of said Complex Mixer;

wherein said Complex Mixer in said baseband mode is clocked by a clock signal equal to an A/D sampling rate, and outputs Inphase and Quadrature outputs for each said clock signal;

and wherein said Complex Mixer in said passband mode is clocked by a clock signal equal to one half of said A/D sampling rate, and outputs Inphase and Quadrature outputs for each said clock signal.

24. An apparatus for demodulating a digital input signal having a pre-assigned symbol rate by using a single sample clock signal; said pre-assigned symbol rate is selected from the group consisting of a plurality of symbol rates; said apparatus comprising:

a means for down converting an input digital signal having said pre-assigned symbol rate signal from a carrier frequency to a baseband frequency;

a means for performing a filtering-decimation operation to isolate a down converted digital signal having said pre-assigned symbol rate; wherein said means for performing said filtering-decimation operation to isolate said down converted digital signal having said pre-assigned symbol rate further includes:

an integer K of parallel Cascaded Integrated Comb CIC integrators;

an integer K of Numerical Control Oscillators (NCO)s;

and

an integer K of CIC mixers;

wherein a K-stage integrator is configured to increase by a K-factor a processing speed of said incoming digital input signal having said pre-assigned data rate;

a means for restoring an original spectrum of a pre-assigned signal;

a means for extracting a frequency component from a restored signal having said original spectrum of said pre-assigned signal;

a means for estimating a frequency offset between a pre-assigned carrier frequency and said frequency component of said restored signal having said original spectrum of said pre-assigned signal;

and

a means for inserting said estimated frequency offset into a carrier loop in order to complete a carrier recovery of said pre-assigned input digital signal;

25. The apparatus of claim 24 wherein said means for performing said filtering-decimation operation to isolate said down converted digital signal having said pre-assigned symbol rate further includes:

at least one Comb filter further including:

an integer M-section cascaded comb filter; and wherein each said section of said M-section cascaded comb filter further includes:

an integer N of registers;

and

a substracter;

and

a decimation block;

and wherein each said section of said M-section cascaded comb filter having said integer N of registers differentiates an integrated output of said K-stage integrator with a combinatorial delay of N samples;

and wherein said decimation block decimates an output signal of said M-section comb filter by a decimation factor R; and wherein said CIC Decimator requires log 2 [(RN)] M additional bits as compared with a number of bits in said input digital data signal to avoid overflow; wherein R is an integer.

26. The apparatus of claim 25 further including:

a means for performing a pipeline computation on a plurality of input symbols in order to increase the speed of operation of each said section of said M-section cascaded comb filter by N-factor by minimizing said combinatorial delay of N samples.

27. The apparatus of claim 25 , wherein said means for performing said adaptive carrier loop frequency adjustment further includes:

a controller configured to generate a control update signal;

a nominal frequency update block electrically communicating with said controller and configured to update a nominal frequency coefficient in said adaptive CIC tuner loop using said control update signal;

a coarse frequency offset update block electrically communicating with said controller and configured to update a coarse frequency offset coefficient in said adaptive CIC tuner loop using said control update signal;

a phase update block electrically communicating with said controller and configured to update a phase coefficient in said adaptive CIC tuner loop using said control update signal;

a frequency accumulator;

and

a phase accumulator.

28. The apparatus of claim 27 , wherein said means for performing said adaptive carrier loop frequency adjustment further includes:

an algorithm comprising at least the following steps:

if a frequency update in said frequency accumulator exceeds a predetermined high frequency threshold; use a plurality of negative frequency coefficients for a next loop frequency update;

if said frequency update in said frequency accumulator is lower than a predetermined low frequency threshold; use a plurality of positive frequency coefficients for said next loop frequency update;

if a phase update in said phase accumulator exceeds a predetermined high phase threshold; use a plurality of negative phase coefficients for a next loop phase update;

and

if said phase update in said phase accumulator is lower than a predetermined low phase threshold; use a plurality of positive phase coefficients for said next phase loop update.