DC offset cancel circuit
View Patent ↗This invention is applied to dual mode provided receiver capable of coinciding with both TDMA system and the non-TDMA system so as to provide a DC offset cancel circuit preferable for each communication method having a compact structure. In case where a predetermined time slot is allocated as an offset quantity detection time in the TDMA system, a first feedback loop is activated and corresponding to detection signals corresponding to differential output signals OUT, XOUT by a comparator 2, a detection result is updated in the holding section 3 according to a strobe signal STB and held therein. Output signals from the holding section 3 are fed back to an amplifier 1 through a selection section 5 and a DC offset is cancelled out. In case where the offset quantity is detected successively, a second feedback loop is activated and then, detection signals from the comparator 2 are identified by a filter section 4, and fed back to the amplifier 1 through the selection portion 5, so that the DC offset is cancelled out.
1. A DC offset cancel circuit for canceling DC offset component included in at least one output signal from a signal processing section that applies signal processing to at least one input signal, the DC offset cancel circuit comprising:
a detecting section for detecting offset quantity of the DC offset component;
a holding section for holding a detection result based on at least one detection signal outputted from the detector section; and
a filter section for distinguishing the DC offset component,
wherein either the holding section or the filter section is activated.
2. A DC offset cancel circuit according to claim 1 further comprising:
a first feedback loop that encompasses the detector section and the holding section and returns to the signal processing section; and
a second feedback loop that encompasses the detecting section and the filter section and returns to the signal processing section,
wherein the detection signal is inputted to the filter section and either the first feedback loop or the second feedback loop is activated.
3. A DC offset cancel circuit according to claim 2 , wherein the filter section includes a lowpass filter or an integration circuit.
4. A DC offset cancel circuit according to claim 1 further comprising:
a first switching section for switching frequency band of the filter section; and
a third feedback loop that encompasses the detecting section, the filter section and the holding section in this order and returns to the signal processing section,
wherein the detection signal is inputted to the filter section.
5. A DC offset cancel circuit according to claim 1 further comprising:
a first bypass path for bypassing the filter section;
a first selecting section for selecting either a first path that goes through the filter section or the first bypass path; and
a fourth feedback loop that encompasses the detecting section, their first path or the first bypass path, and the holding section in this order and returns to the signal processing section,
wherein the detection signal is inputted to the filter section.
6. A DC offset cancel circuit according to claim 1 further comprising a feedback loop that encompasses the detecting section and the holding section and returns to the signal processing section, wherein the output signal is inputted to the filter section.
7. A DC offset cancel circuit according to claim 6 further comprising a second switching section for switching frequency band of the filter section.
8. A DC offset cancel circuit according to claim 6 further comprising:
a second bypass path for bypassing the filter section;
a second selecting section for selecting either a second path that goes through the filter section or the second bypass path.
9. A DC offset cancel circuit according to claim 6 , wherein the filter section includes a highpass filter.
10. A DC offset cancel circuit according to claim 1 , wherein the holding section holds a correction value of the DC offset component obtained through signal processing in accordance with the detection signal as the detection result.
11. A DC offset cancel circuit according to claim 10 , wherein the signal processing is equivalent to digital signal processing and the correction value is a digitalized value.
12. A DC offset cancel circuit according to claim 10 , wherein the correction value is renewed by a trigger signal.
13. A DC offset cancel circuit according to claim 10 , wherein, in case the holding section is in a non-active state, the holding section does not hold the correction value.
14. A DC offset cancel circuit according to claim 1 , wherein the signal processing section includes an amplifier.
15. A DC offset cancel circuit according to claim 1 , wherein the signal processing section includes an active filter.