Method and system for time domain multiplexers with reduced inter-symbol interference
View Patent ↗Method and system for a high-speed multiplexer with reduced inter-symbol interference are disclosed. In one embodiment of the present invention, two input bit streams are interleaved by a multiplexer to derive an output bit stream. Each input bit stream is latched by a return-to-differential-zero latch that drives its input bit stream to a neutral state when it is not selected by the multiplexer as output. In an alternate embodiment of the present invention, a pre-selector receives two input signals, determines which of the two input signals will be selected as output of the multiplexer and passes the bit stream unaltered, while passing a differential zero value in place of the unselected input bit stream.
1. A multiplexer, comprising:
a first latch having a first input for receiving a first bit stream and a second input for receiving a clock signal, wherein the first latch is an edge-triggered latch clocked in phase when the clock signal transitions into a first polarity to transmit input data from the first data stream, and latch the input data when the clock signal transitions into a second polarity;
a first return-to-differential-zero latch coupled to the first latch, the first return-to-differential-zero latch having a first input for receiving an output of the first latch and a second input for receiving a clock signal,
wherein the first return-to-differential-zero latch is an edge-triggered latch clocked in phase when the clock signal transitions into a second polarity to transmit output data from the first latch, and
wherein the first return-to-differential-zero latch has an output comprising the value of the output of the first latch when the first return-to-differential zero latch receives a clock signal of the second polarity and comprising a neutral value when the first return-to-differential-zero latch receives a clock signal of the first polarity;
a second return-to-differential-zero latch having a first input for receiving a second bit stream and a second input for receiving a clock signal, wherein the second return-to-differential-zero latch is an edge-triggered latch clocked in phase when the clock signal transitions into the first polarity to transmit input data from the second bit stream; and
a selector having a first input coupled to the output of the first return-to-differential-zero latch and a second input coupled to the output of the second return-to-differential-zero latch, and a third input for receiving a select input signal.
2. The multiplexer of claim 1 , wherein the second return-to-differential-zero latch having an output comprising the value of the second data stream input when the second return-to-differential-zero latch receives a clock signal of the first polarity, and comprising a neutral value when the second return-to-differential-zero latch receives a clock signal of the second polarity.
3. The multiplexer of claim 2 , wherein the select input signal comprising a value inverse to that of the clock signal; such that the output of the first return-to-differential-zero latch is passed to the selector output when receiving a clock signal of the second polarity; and the output of the second return-to-differential-zero latch is passed to the selector output when receiving a clock signal of the first polarity.
4. The multiplexer of claim 3 , wherein the selector having an output data bit stream.
5. The multiplexer of claim 4 , wherein the output data bit stream is a result of interleaving the data bits of the first bit stream with the data bits of the second bit stream.
6. A multiplexer, comprising:
a first latch having a first input for receiving a first bit stream and a second input for receiving a clock signal, wherein the first latch is an edge-triggered latch clocked in phase when the clock signal transitions into a first polarity to transmit input data from the first data stream, and latch the input data when the clock signal transitions into a second polarity;
a pre-selector coupled to the first latch, the pre-selector having a first input for receiving an output of the first latch, a second input for receiving a second bit stream, a third input for receiving a first select input signal comprising the value of the clock signal, a first output, and a second output,
wherein the first output comprising the value of the output of the first latch and the second output comprising a neutral value when the pre-selector receives a clock signal of the second polarity, and
wherein the second output comprising the value of the second bit stream and the first output comprising a neutral value when the pre-selector receives a clock signal of the first polarity; and
a selector coupled to the pre-selector, the selector having a first input for receiving a first output of the pre-selector, a second input for receiving a second output of the pre-selector, and a third input for receiving a second select input signal.
7. The multiplexer of claim 6 , wherein the second select input signal comprising a value inverse to that of the clock signal; such that the first output of pre-selector is passed to the selector output when receiving a clock signal of the second polarity; and the output of the second output of the pre-selector is passed to the selector output when receiving a clock signal of the first polarity.
8. The multiplexer of claim 7 , wherein the selector having an output data bit stream.
9. The multiplexer of claim 8 , wherein the output data bit stream is a result of interleaving the data bits of the first bit stream with the data bits of the second bit stream.