Printed circuit board noise attenuation using lossy conductors
View Patent ↗A method and related configuration for attenuating high-frequency noise that may appear on power planes in printed circuit boards. In one embodiment, the noise attenuation means of the present invention involves applying a lower conductivity material between the conductive and dielectric layers within a printed circuit board. High-frequency noise is then attenuated by the skin effect. In another embodiment, the low conductivity material is applied between the power plane and dielectric layer within the printed circuit board. The low conductivity material may be a material, such as nickel or lead, having an electrical conductivity ranging between about 1×10 4 mhos/m and 5.8×10 7 mhos/m for layers having a thickness of about 2 mils.
1. A method for attenuating noise on a printed circuit board comprising:
applying a laminate between a conductive layer and a dielectric layer of the printed circuit board, wherein the laminate is a lossy conductor with an electrical conductivity less than that of the conductive layer, and wherein the laminate is globally applied across the conductive and dielectric layers wherein the laminate has an electrical conductivity between about 1×10 4 mhos/meter and about 5.8×10 7 mhos/meter.
2. The method of claim 1 wherein the conductive layer is a plane in a set consisting of a power plane and a ground plane.
3. The method of claim 1 wherein two adjacent conductive layers comprise a power and ground plane pair, the conductive layers separated by a dielectric layer, wherein a laminate is sandwiched between the dielectric and at least one of the conductive layers.
4. The method of claim 1 wherein the laminate includes a material in a set consisting of lead, phosphorus and tin.
5. The method of claim 1 wherein the laminate has a thickness equal to or less than that of the conductive layer.
6. A method for attenuating noise on a printed circuit board comprising:
applying a laminate between a conductive layer and a dielectric layer of the printed circuit board, wherein the laminate is a lossy conductor with an electrical conductivity less than that of the conductive layer, wherein the laminate has an electrical conductivity between about 1×10 4 mhos/meter and about 5.8×10 7 mhos/meter.
7. A method for attenuating noise on a printed circuit board comprising:
applying a laminate between a conductive layer and a dielectric layer of the printed circuit board, wherein the laminate is a lossy conductor with an electrical conductivity less than that of the conductive layer wherein the laminate has a maximum thickness of about 2 mils wherein the laminate has an electrical conductivity between about 1×10 4 mhos/meter and about 5.8×10 7 mhos/meter.
8. A printed circuit board comprising:
a conductive layer;
a dielectric layer;
a laminate located between the conductive layer and the dielectric layer, wherein the laminate material is a lossy conductor with an electrical conductivity less than that of the conductive layer, and wherein the laminate is globally applied across the conductive and dielectric layers wherein the laminate has an electrical conductivity between about 1×10 4 mhos/meter and about 5.8×10 7 mhos/meter.
9. The printed circuit board of claim 8 wherein the conductive layer is a plane in a set consisting of a power plane and a ground plane.
10. The printed circuit board of claim 8 wherein the laminate includes a material in a set consisting of lead, phosphorus and tin.
11. The printed circuit board of claim 8 wherein the laminate has a thickness equal to or less than that of the conductive layer.
12. A printed circuit board comprising:
a conductive layer;
a dielectric layer;
a laminate located between the conductive layer and the dielectric layer, wherein the laminate material is a lossy conductor with an electrical conductivity less than that of the conductive layer, wherein the laminate has an electrical conductivity between about 1×10 4 mhos/meter and about 5.8×10 7 mhos/meter.
13. An EMI-reducing circuit board structure that comprises:
a dielectric layer having a first surface;
circuit traces patterned on said first surface, wherein the circuit traces each include:
a first layer of conductive material; and
a second layer of low-conductivity material that contacts the first layer, wherein the low-conductivity material has a conductivity between about 0.1% and 50% of the conductive material.
14. A packaging substrate for integrated circuits comprising:
a conductive layer;
a dielectric layer;
a laminate located between the conductive layer and the dielectric layer, wherein the laminate material is a lossy conductor with an electrical conductivity less than that of the conductive layer, and wherein the laminate is globally applied across the conductive and dielectric layers wherein the laminate has an electrical conductivity between about 1×10 4 mhos/meter and about 5.8×10 7 mhos/meter.
15. The packaging substrate of claim 14 wherein the conductive layer is a plane in a set consisting of a power plane and a ground plane.
16. The packaging substrate of claim 14 wherein the laminate is a material in a set consisting of lead, phosphorus and tin.
17. The packaging substrate of claim 14 wherein the laminate has a thickness equal to or less than that of the conductive layer.
18. A packaging substrate for integrated circuits comprising:
a conductive layer;
a dielectric layer;
a laminate located between the conductive layer and the dielectric layer, wherein the laminate material is a lossy conductor with an electrical conductivity less than that of the conductive layer, wherein the laminate has an electrical conductivity between about 1×10 4 mhos/meter and about 5.8×10 7 mhos/meter.
19. An apparatus for connecting electrical devices, comprising:
a conductor layer;
a laminate layer globally disposed about the conductor layer; and
an insulator layer globally disposed about the laminate layer, wherein the electrical conductivity of the laminate layer is less than the conductivity of the insulator layer, wherein the laminate layer comprises phosphorus.
20. A semiconductor package for integrated circuits comprising:
a substrate for electrically interconnecting with an integrated circuit, the substrate comprising at least one conductive layer and at least one dielectric layer, wherein a laminate is globally distributed between the conductive layer and the dielectric layer, and wherein the laminate material is a lossy conductor with an electrical conductivity less than that of the conductive layer wherein the laminate has an electrical conductivity between about 1×10 4 mhos/meter and about 5.8×10 7 mhos/meter.
21. The semiconductor package of claim 20 wherein the conductive layer is a plane in a set consisting of a power plane and a ground plane.
22. The semiconductor package of claim 20 wherein the laminate includes a material in a set consisting of lead, phosphorus and tin.
23. The semiconductor package of claim 20 wherein the laminate has a thickness equal to or less than that of the conductive layer.
24. A semiconductor package for integrated circuits comprising:
a substrate for electrically interconnecting with an integrated circuit, the substrate comprising at least one conductive layer and at least one dielectric layer, wherein a laminate is sandwiched between the conductive layer and the dielectric layer, wherein the laminate material is a lossy conductor with an electrical conductivity less than that of the conductive layer, and wherein the laminate has an electrical conductivity between about 1×10 4 mhos/meter and about 5.8×10 7 mhos/meter.
25. An apparatus for connecting electrical devices, comprising:
a conductor layer;
a laminate layer globally disposed about the conductor layer; and
an insulator layer globally disposed about the laminate layer, wherein the
electrical conductivity of the laminate layer is less than the conductivity of the insulator layer, wherein the laminate layer has a conductivity between about 0.1% and 50% of the conductor layer.
26. An EMI-reducing circuit board structure that comprises:
an dielectric layer having a first surface;
circuit traces patterned on said first surface, wherein the circuit traces each include:
a first layer of conductive material; and
a second layer of low-conductivity material that globally contacts the first layer wherein the second layer has an electrical conductivity between about 1×10 4 mhos/meter and about 5.8×10 7 mhos/meter.
27. The structure of claim 26 , wherein the second layer lies between the first layer and the dielectric layer.
28. The structure of claim 26 , wherein the low-conductivity material has a conductivity less than that of the conductive material.
29. The structure of claim 26 , further comprising:
a second set of circuit traces patterned on a second surface of the dielectric layer opposite the first surface.
30. The structure of claim 29 , wherein the second set of circuit traces includes:
a first layer of conductive material; and
a second layer of low-conductivity material that contacts the first layer.
31. The structure of claim 30 , wherein the layer of low-conductivity material in the second set of circuit traces lies between the dielectric layer and the layer of conductive material in the second set of circuit traces.
32. An apparatus for connecting electrical devices, comprising:
a conductor layer;
a laminate layer globally disposed about the conductor layer; and
an insulator layer globally disposed about the laminate layer, wherein the electrical conductivity of the laminate layer is less than the conductivity of the conductor layer but greater than the conductivity of the insulator layer wherein the laminate has an electrical conductivity between about 1×10 4 mhos/meter and about 5.8×10 7 mhos/meter.
33. The apparatus of claim 32 , wherein the laminate layer comprises lead.
34. The apparatus of claim 32 , wherein the laminate layer comprises tin.