Method and a system for using same set of registers to handle both single and double precision floating point instructions in an instruction stream

1. A method for handling a plurality of single precision floating point instructions and a plurality of double precision floating point instructions in a fetch group without conflict in registers,

wherein the method utilizes a decode unit comprising:

a first counter arranged to increment for at least one of the plurality of single precision floating point instructions forwarded, without regard to double precision floating point instructions forwarded;

a second counter arranged to increment for at least one of the plurality of double precision floating point instructions forwarded, without regard to single precision floating point instructions forwarded;

a first mask register indexed by single precision registers, wherein the first mask register is updated by at least one of the plurality of single precision floating point instructions forwarded, without regard to double precision floating point instructions forwarded; and

a second mask register indexed by double precision registers, wherein the second mask register is updated by at least one of the plurality of double precision floating point instructions forwarded, without regard to single precision floating point instructions forwarded,

wherein the method comprises:

decoding at least one of the plurality of the single precision floating point instructions and at least one of the plurality of the double precision floating point instructions;

evaluating the at least one of the plurality of the single precision floating point instructions and the at least one of the double precision floating point instructions in the fetch group, wherein the evaluating is based on values of the first counter and the second counter and based on a value of an entry in the first mask register and a value of an entry in the second mask register; and

based on the evaluating, processing the at least one of the plurality of the single precision floating point instructions and the at least one of the plurality of the double precision floating point instructions.

2. The method of claim 1 , wherein the evaluating comprises:

determining values of the first counter and the second counter;

determining whether the at least one of the plurality of the single precision floating point instructions is younger than a double precision floating point instruction in the fetch group and whether a source register of the at least one of the plurality of the single precision floating point instructions references a destination register of the double precision floating point instruction; and

if the first and the second counters are non-zero, determining whether the value of the entry in the second mask register corresponding to the source register of the single precision floating point instruction is indexed with a particular logic value.

3. The method of claim 2 , wherein the processing comprises:

forwarding the at least one of the plurality of the single precision floating point instructions;

incrementing the first counter; and

updating a value of an entry in the first mask register.

4. The method of claim 2 , wherein the processing comprises:

committing the at least one of the plurality of the single precision floating point instructions; and

decrementing the first counter, and if the first counter reaches zero, clearing the first mask register.

5. The method of claim 2 , wherein the processing comprises stalling the at least one of the plurality of the single precision floating point instructions.

6. The method of claim 1 , wherein the evaluating comprises:

determining values of the first counter and the second counter;

determining whether the at least one of the plurality of the double precision floating point instructions is younger than a single precision floating point instruction in the fetch group and whether a source register of the at least one of the plurality of the double precision floating point instructions references a destination register of the single precision floating point instruction; and

if the first and the second counters are non-zero, determining whether the value of the entry in the first mask register corresponding to the source register of the double precision floating point instruction is indexed with a particular logic value.

7. The method of claim 6 , wherein the processing comprises:

forwarding the at least one of the plurality of the double precision floating point instructions;

incrementing the second counter; and

updating a value of an entry in the second mask register.

8. The method of claim 6 , wherein the processing comprises:

committing the at least one of the plurality of the double precision floating point instructions; and

decrementing the second counter, and if the second counter reaches zero, clearing the second mask register.

9. The method of claim 6 , wherein the processing comprises stalling the at least one of the plurality of the double precision floating point instruction.

10. The method of claim 1 , wherein the first mask comprises a thirty-two entry mask.

11. The method of claim 1 , wherein the thirty-two entry mask corresponds to thirty-two single precision registers.

12. The method of claim 1 , wherein the second mask comprises a sixteen entry mask.

13. The system of claim 1 , wherein the sixteen entry mask corresponds to sixteen double precision registers.

14. A method for handling a plurality of single precision and a plurality of double precision floating point instructions without conflict in registers,

wherein the method utilizes a decode unit comprising:

a first counter arranged to increment for at least one of the plurality of single precision floating point instructions forwarded, without regard to double precision floating point instructions forwarded;

a second counter arranged to increment for at least one of the plurality of double precision floating point instructions forwarded, without regard to single precision floating point instructions forwarded;

a first mask register indexed by single precision registers, wherein the first mask register is updated by at least one of the plurality of single precision floating point instructions forwarded, without regard to double precision floating point instructions forwarded; and

a second mask register indexed by double precision registers, wherein the second mask register is updated by at least one of the plurality of double precision floating point instructions forwarded, without regard to single precision floating point instructions fowarded,

wherein the method comprises:

step for decoding at least one of the plurality of the single precision floating point instructions and at least one of the plurality of the double precision floating point instructions;

step for evaluating the at least one of the plurality of the single precision floating point instructions and the at least one of the plurality of the double precision floating point instructions in the fetch group, wherein the step for evaluating is based on values of the first counter and the second counter and based on indexing of the first mask register and the second mask register; and

based on the step for evaluating, step for processing the at least one of the plurality of the single precision floating point instructions and the at least one of the plurality double precision floating point instructions.

15. The method of claim 14 , wherein the step for evaluating comprises:

step for determining values of the first counter and the second counter;

step for determining whether the at least one of the plurality of the single precision floating point instructions is younger than a double precision floating point instruction in the fetch group and whether a source register of the at least one of the plurality of the single precision floating point instructions references a destination register of the double precision floating point instruction; and

if the first and the second counters are non-zero, step for determining whether the value of the entry in the second mask register corresponding to the source register of the single precision floating point instruction is indexed with a particular logic value.

16. The system of claim 15 , wherein the step for processing comprises:

step for forwarding the at least one of single precision floating point instructions;

step for incrementing the first counter; and

step for updating a value of an entry in the first mask register.

17. The system of claim 15 , wherein the step for processing comprises:

step for committing the at least one of the single precision floating point instructions; and

step for decrementing the first counter, and if the first counter reaches zero, step for clearing the first mask register.

18. The system of claim 15 , wherein the step for processing comprises step for stalling the at least one of the single precision floating point instructions.

19. The method of claim 14 , wherein the step for evaluating comprises:

step for determining values of the first counter and the second counter;

step for determining whether the at least one of the plurality of the double precision floating point instructions is younger than a single precision floating point instruction in the fetch group and whether a source register of the at least one of the plurality of the double precision floating point instructions references a destination register of the single precision floating point instruction; and

if the first and the second counters are non-zero, step for determining whether the value of the entry in the first mask register corresponding to the source register of the double precision floating point instruction is indexed with a particular logic value.

20. The system of claim 19 , wherein the step for processing comprises:

step for forwarding the at least one of the double precision floating point instructions;

step for incrementing the second counter; and

step for updating a value of an entry in the second mask register.

21. The system of claim 19 , wherein the step for processing comprises:

step for committing the at least one of the double precision floating point instructions; and

step for decrementing the second counter, and if the second counter reaches zero, step for clearing the second mask register.

22. The method of claim 19 , wherein the step for processing comprises a step for stalling the at least one of the double precision floating point instructions.