System and method for clock independent pulse width modulation
View Patent ↗A method of clocking a video processing circuit is performed by stalling a reference clock signal. The reference clock signal is stalled based on a stall signal from a clock-independent pulse width modulator. The stalled reference clock signal is used to produce a video clock signal for use by an image data processing circuit.
1. A video processing system for a laser printer, comprising:
a video image formatter;
a clock-independent pulse width modulator; and
a clock gating circuit configured to provide a clock signal to said video image formatter based on a stall signal received from said clock-independent pulse width modulator.
2. The video processing system of claim 1 , wherein said video image formatter converts raw image data into binary pulse width code and outputs said binary pulse width code to said clock-independent pulse width modulator.
3. The video processing system of claim 2 , wherein said video image formatter comprises a video data path controlled by a video control block, wherein said clock signal is provided to said video control block.
4. The video processing system of claim 1 , wherein said clock gating circuit receives and stalls a reference clock signal to produce said clock signal.
5. The video processing system of claim 4 , wherein said clock gating circuit comprises a D flip-flop and a logic OR gate.
6. The video processing system of claim 4 , wherein said reference clock signal is also provided to a control block of said clock-independent pulse width modulator.
7. The video processing system of claim 6 , wherein said reference clock signal is also provided to a pulse width modulator of said clock-independent pulse width modulator.
8. The video processing system of claim 1 , wherein said clock-independent pulse width modulator comprises a first-in-first-out (FIFO) buffer, a pulse width modulator receiving data from said FIFO buffer, and control block for controlling said FIFO buffer and said pulse width modulator.
9. The video processing system of claim 8 , wherein said clock-independent pulse width modulator outputs a modulating signal to a laser.
10. The video processing system of claim 9 , further comprising a laser print engine comprising said laser.
11. A clock gating circuit for clocking video processing circuitry, comprising:
an input for receiving a reference clock signal;
an input for receiving a stall signal from a clock-independent pulse width modulator; and
a gating circuit configured to alter said reference clock signal in accordance with said stall signal and output a resulting video clock signal for said video processing circuitry.
12. The clock gating circuit of claim 11 , wherein said gating circuit comprises a D flip-flop and a logic OR gate.
13. The clock gating circuit of claim 12 , wherein:
said D flip-flop receives said stall signal and said reference clock signal and outputs a signal to one input of said OR gate;
said OR gate receives said reference clock and said signal output by said flip-flop and outputs said video clock signal.
14. The clock gating circuit of claim 11 , said gating circuit alters said reference clock signal by stalling the reference clock signal.
15. The clock gating circuit of claim 11 , wherein said reference clock signal is derived from a system clock of a laser printer.
16. A method of clocking a video processing circuit, said method comprising stalling a reference clock signal based on a stall signal from a clock-independent pulse width modulator to produce a video clock signal for use by an image data processing circuit.
17. The method of claim 16 , further comprising:
placing a clock gating circuit between a reference clock and said image data processing circuit; and
stalling said reference clock signal with said clock gating circuit.
18. The method of claim 16 , further comprising inputting said stall signal to said clock gating circuit with said clock-independent pulse width modulator.
19. The method of claim 16 , further comprising stalling said reference clock signal with a D flip-flop and a logic OR gate.
20. The method of claim 19 , further comprising:
inputting said stall signal and said reference clock signal to said D flip-flop;
inputting said reference clock and an output of said D flip-flop to said OR gate; and
outputting said video clock signal from said OR gate.
21. The method of claim 16 , further comprising deriving said reference clock signal from a system clock signal of a laser printer.
22. The method of claim 16 , further comprising processing image data with said image data processing circuit according to a timing of said video clock signal.
23. A method of printing comprising:
clocking a video processing circuit by stalling a reference clock signal based on a stall signal from a clock-independent pulse width modulator to produce a video clock signal for use by an image data processing circuit; and
processing image data with said image data processing circuit according to a timing of said video clock signal.
24. The method of claim 23 , further comprising:
placing a clock gating circuit between a reference clock and said image data processing circuit; and
stalling said reference clock signal with said clock gating circuit.
25. The method of claim 23 , further comprising inputting said stall signal to said clock gating circuit with clock-independent pulse width modulator.
26. The method of claim 23 , further comprising staling said reference clock signal with a D flip-flop and a logic OR gate.
27. The method of claim 26 , further comprising:
inputting said stall signal and said reference clock signal to said D flip-flop;
inputting said reference clock and an output of said D flip-flop to said OR gate; and
outputting said video clock signal from said OR gate.
28. The method of claim 23 , further comprising deriving said reference clock signal from a system clock signal of a laser printer.
29. The method of claim 23 , further comprising processing image data with said image processing circuit according to a timing of said video clock signal.
30. The method of claim 23 , further comprising:
receiving a binary pulse width code from said image data processing circuit; and
producing a modulation signal from said binary pulse width code with said clock-independent pulse width modulator.
31. The method of claim 30 , further comprising modulating a laser with said modulation signal to print an image corresponding to said image data.
32. A system for printing comprising:
image data processing means for processing image data; and
means for stalling a reference clock signal based on a stall signal from a clock-independent pulse width modulator to produce a video clock signal for use by said image data processing means.
33. The system of claim 32 , further comprising means for inputting said stall signal to said clock gating circuit from said clock-independent pulse width modulator.
34. The system of claim 32 , wherein:
said means for stalling further comprise a D flip-flop and a logic OR gate;
said D flip-flop receives said stall signal and said reference clock signal and outputs a signal to one input of said OR gate; and
said OR gate receives said reference clock and said signal output by said flip-flop and outputs said video clock signal.
35. The system of claim 32 , further comprising means for deriving said reference clock signal from a system clock signal of a laser printer.
36. The system of claim 32 , wherein said clock-independent pulse width modulator comprises:
means for receiving a binary pulse width code from said image data processing means; and
means for producing a modulation signal from said binary pulse width code.
37. The system of claim 36 , further comprising means for modulating a laser with said modulation signal to print an image corresponding to said image data.
38. A video processing system for a laser printer comprising:
a video image formatter comprising a video control block; and
a clock-independent pulse width modulator configured to output a stall signal based on operation of said clock-independent pulse width modulator.
wherein said video control block is configured to provide a clock signal for said video image formatter based on said stall signal received from said clock-independent pulse width modulator.
39. The video processing system of claim 38 , wherein said video image formatter converts raw video image into binary pulse width code and outputs said binary pulse width code to said clock-independent pulse with modulator.
40. The video processing system of claim 39 , wherein said video image formatter comprises a video path controlled by said video control block, wherein said clock signal is provided to said data path.
41. The video processing system of claim 38 , wherein said clock-independent pulse width modulator comprises a first-in-first-out (FIFO) buffer, a pulse width modulator receiving data from said FIFO buffer, and control block for controlling said FIFO buffer and said pulse width modulator.
42. The video processing system of claim 38 , wherein said clock-independent pulse width modulator outputs a modulating signal to a laser.
43. The video processing system of claim 42 , further comprising a laser print engine comprising said laser.