Methods and circuits for balancing bitline precharge
View Patent ↗A memory array design is provided. Memory cells are defined an intersections of rows and columns. A pair of bitline segments are defined for each column. A connecting load device of each memory cell is connected to either a first or a second of the pair of bitline segments. An equal number of load devices in each column couple to each of the pair of bitlines.
1. A memory device, comprising:
an array having a series of storage cells, the storage cells being arranged in rows and columns;
a pair of bitline segments defined for each column, wherein a first of the pair of bitline segments is coupled to an even one of the rows and a second of the pair of bitline segments is coupled to an odd one of the rows; and
a pair of precharge devices, a first of the pair of precharge devices being coupled to the first of the pair of bitline segments and a second of the pair of precharge devices being coupled to the second of the pair of bitline segments, each of the pair of precharge devices being separately coupled to its respective bitline segment and without coupling the pair of precharge devices.
2. A memory device as recited in claim 1 , further comprising:
even numbered storage devices of even rows being coupled to the first of the pair of bitlines; and
odd numbered storage devices of odd rows being coupled to the second of the pair of bitlines.
3. A memory device as recited in claim 2 , further comprising:
even numbered load devices interconnecting the even numbered storage devices to the first of the pair of bitlines; and
odd numbered load devices interconnecting the odd numbered storage devices to the second of the pair of bitlines.
4. A memory device as recited in claim 3 , wherein the even numbered load devices and the odd numbered load devices define an equal number of load devices connected to each of the first of the pair of bitlines and the second of the pair of bitlines, the equal number establishing a balanced load on the pair of bitlines.
5. A memory device as recited in claim 1 , wherein each of the bitline segments has about an equal length and carries an equal number of load devices to produce a substantially balanced precharge delay of each column of the memory device.
6. A memory device as recited in claim 1 , further comprising: logic for combining a signal output of the bitline segments.
7. A memory device as recited in claim 6 , further comprising:
an amplifier for amplifying an output generated by the logic for combining the signal output of the bitline segments.
8. A memory device as recited in claim 6 , wherein the logic for combining the signal output of the bitline segments includes AND logic circuitry.
9. A memory device, comprising:
an array having a series of storage cells, the storage cells being arranged in rows and columns;
a pair of bitline segments defined for each column, wherein a first of the pair of bitline segments is coupled to an even one of the rows and a second of the pair of bitline segments is coupled to an odd one of the rows; and
a pair of precharge devices, a first of the pair of precharge devices being coupled to the first of the pair of bitline segments and a second of the pair of precharge devices being coupled to the second of the pair of bitline segments, wherein the pair of precharge devices are not coupled to each other;
wherein even numbered load devices and odd numbered load devices define an equal number of load devices connected to each of the first of the pair of bitlines and the second of the pair of bitlines, the equal number establishing a substantially balanced load on a bitline column that is defined by the pair of bitlines.
10. A memory device as recited in claim 9 , wherein each of the bitline segments has about an equal length and carries an equal number of load devices to produce a substantially balanced precharge delay of each column of the memory device.
11. A memory device as recited in claim 9 , further comprising: logic for combining a signal output of the bitline segments.
12. A memory device as recited in claim 11 , further comprising:
an amplifier for amplifying an output generated by the logic for combining the signal output of the bitline segments.
13. A memory device as recited in claim 11 , wherein the logic for combining the signal output of the bitline segments includes AND logic circuitry.
14. A memory array, comprising:
memory cells defined an intersections of rows and columns;
a pair of bitline segments defined for each column; and
a connecting load device of each memory cell being connected to either a first or a second of the pair of bitline segments, wherein an equal number of load devices in each column couple to each of the pair of bitlines; and
a pair of precharge devices, each of the pair of precharge devices being coupled to the pair of bitlines in each column, wherein the pair of precharge devices are not coupled together.
15. A memory array as recited in claim 14 , wherein the memory array is a banked memory array.
16. A memory array as recited in claim 14 , further comprising:
combining logic for combining an output of each of the pair of bitlines.
17. A memory array as recited in claim 16 , an amplifier for receiving an output of the combining logic of each column.
18. A memory array as recited in claim 16 , wherein the combining logic includes AND logic.
19. A memory array as recited in claim 17 , wherein the amplifier is an operational amplifier.