Frequency comparator with hysteresis between locked and unlocked conditions
View Patent ↗A frequency comparator apparatus used with a reference clock, a voltage controlled oscillator circuit and a phase locked loop circuit includes a reference loop circuit wherein the reference loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is greater than about a first threshold. Also included is a data loop circuit wherein the data loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is less than about a second threshold.
1. A frequency comparator apparatus used with a reference clock, a voltage controlled oscillator circuit and a phase locked loop circuit comprising:
a reference loop circuit wherein the reference loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is greater than about a first threshold; and
a data loop circuit; wherein the data loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is less than about a second threshold.
2. The frequency comparator apparatus as in claim 1 wherein the first threshold is 1000 parts per million.
3. The frequency comparator apparatus as in claim 1 wherein the second threshold is 200 parts per million.
4. A frequency comparator apparatus as in claim 1 wherein the frequency comparator is designed to have a hysteresis that closely matches the capture and lock range of the phase locked loop circuit.
5. A frequency comparator apparatus as in claim 1 wherein the frequency comparator operates as a frequency acquisition aid.
6. A frequency comparator apparatus as in claim 1 wherein the frequency comparator drives the voltage controlled oscillator frequency toward the reference clock frequency.
7. A frequency comparator apparatus as in claim 1 wherein the reference loop circuit is activated when the frequency comparator is in an unlocked state.
8. A frequency comparator apparatus as in claim 1 wherein the data loop circuit is activated when the frequency comparator is in a locked state.
9. A frequency comparator apparatus as in claim 1 wherein the lock range of the frequency comparator is less than a capture range of the phase locked loop circuit.
10. A receiver apparatus comprising
a phase locked loop circuit including a voltage controlled oscillator used to generate a data sampling clock signal;
a data sampler to receive the data sampling clock signal, to sample a data signal using the data sampling clock signal, and to output sampled data representing a first zone, a second zone, and a third zone of the data signal;
a phase detector to examine the sampled data, to determine which zone of the sampled data has a transition of the data signal, and to output a phase detector signal indicating a direction of change for the data sampling clock signal if the first zone or the third zone has the transition; and
a frequency comparator that compares the frequencies of the data sampling clock produced by the voltage controlled oscillator and a reference clock signal.
11. The receiver of claim 10 , wherein the frequency comparator drives the data sampling clock frequency toward the reference clock signal frequency.
12. The receiver of claim 10 , wherein the frequency comparator acts as a frequency acquisition aid.
13. The receiver of claim 10 , wherein the frequency comparator is designed to have a hysteresis that closely matches the capture and lock range of the phase locked loop circuit.
14. The receiver of claim 10 , wherein the frequency comparator contains a reference loop circuit; wherein the reference loop circuit is activated when the frequency difference between the reference clock and the data sampling clock signal is greater than about a first threshold.
15. The receiver of claim 14 , wherein the first threshold is 1000 parts per million.
16. The receiver of claim 10 , wherein the frequency comparator contains a data loop circuit; wherein the data loop circuit is activated when the frequency difference between the reference clock and the data sampling clock signal is less than about a first threshold.
17. The receiver of claim 16 , wherein the first threshold is 200 parts per million.
18. A method of controlling a receiver to receive data comprising the steps of:
generating a data sampling clock signal;
sampling a data signal using the data sampling clock signal, and outputting sampled data representing a first zone, a second zone, and a third zone of the data signal;
detecting the sampled data, to determine which zone of the sampled data has a transition of the data signal, and to output a phase detector signal indicating a direction of change for the data sampling clock signal if the first zone or the third zone has the transition; and
comparing the frequencies of the data sampling clock and a reference clock signal.
19. The method of claim 18 , wherein the step of comparing drives the data sampling clock frequency toward the reference clock signal frequency.
20. The method of claim 18 , wherein the step of comparing acts as a frequency acquisition aid.
21. The method of claim 18 , wherein the step of comparing is designed to have a hysteresis that closely matches range of the data sampling clock signal.
22. The method of claim 18 , wherein the step of comparing contains a reference loop step; wherein the reference loop step is performed when the frequency difference between the reference clock and the sampling clock signal is greater than about a first threshold.
23. The method of claim 22 , wherein the first threshold is 1000 parts per million.
24. The method of claim 18 , wherein the step of comparing contains a data loop step; wherein the data loop step is performed when the frequency difference between the reference clock and the data sampling clock signal is less than about a first threshold.
25. The method of claim 24 , wherein the first threshold is 200 parts per million.