Compiling and linking modules of a cycle-based logic design

1. A compilation system, comprising:

a cycle-based logic design comprising a plurality of modules, wherein each of the plurality of modules describes a combinational logic component of the cycle-based logic design having an input port and an output port;

a plurality of compilers configured to generate a plurality of object files by compiling the plurality of modules, wherein each of the plurality of compilers inputs one of the plurality of modules and an input file, wherein at least one of the plurality of object files comprises a body code section and an external linkage information section; and

a linker that links the plurality of object files into an executable file for simulating the cycle-based logic design, wherein the executable file is stored as a data structure defined for a massively parallel processor environment.

2. The compilation system of claim 1 , wherein the body code section comprises fixed instructions used during computation of the cycle-based logic design.

3. The compilation system of claim 1 , wherein the external linkage information section comprises information regarding communication between the plurality of modules.

4. The compilation system of claim 3 , wherein the communication between the plurality of modules comprises a description of at least one selected from a group consisting of the input port and the output port.

5. The compilation system of claim 1 , wherein the input file comprises user defined interface files, test vector files, clock files, and port description files.

6. The compilation system of claim 1 , wherein the cycle-based logic design comprises a plurality of top-level modules.

7. The compilation system of claim 1 , wherein the cycle-based logic design comprises a top-level module and a plurality of sub-modules.

8. The compilation system of claim 1 , wherein the cycle-based logic design comprises a user defined plurality of modules.

9. The compilation system of claim 1 , wherein the linker links the plurality of object files during execution.

10. A method for compiling a cycle-based logic design, comprising:

inputting a plurality of modules of the cycle-based logic design and an input file into a plurality of compilers, wherein each of the pluraliw of modules describes a combinational logic component of the cycle-based logic design having an input port and an output port;

compiling separately the plurality of modules to generate a plurality of object files, wherein at least one of the plurality of object files comprises a body code section and an external linkage information section; and

linking the plurality of object files to generate an executable file for simulating the cycle-based logic design, wherein the executable file is stored as a data structure defined for a massively parallel processor environment.

11. The method of claim 10 , wherein the body code section comprises fixed instructions used during computation of the cycle-based logic design.

12. The method of claim 11 , further comprising: using the fixed instructions during computation of the cycle-based logic design.

13. The method of claim 10 , wherein the external linkage information section comprises information regarding communication between the plurality of modules.

14. The method of claim 13 , wherein the communication between the plurality of modules comprises at least one selected from a group consisting of the input port and the output port.

15. The method of claim 10 , wherein the input file comprises user defined interface files, test vector files, clock files, and port description files.

16. The method of claim 10 , wherein the cycle-based logic design comprises a plurality of top-level modules.

17. The method of claim 10 , wherein the cycle-based logic design comprises a top-level module and a plurality of sub-modules.

18. The method of claim 10 , wherein the cycle-based logic design comprises a user defined plurality of modules.

19. The method of claim 10 , wherein the linking occurs during execution.

20. The method of claim 10 , further comprising:

computing a new major cycle using the executable file;

executing the body code section during a computation portion of the new major cycle; and

executing the external linkage information section during a linkage portion of the new major cycle.

21. The method of claim 20 , wherein the executing the external linkage information occurs before the executing the body code section.

22. The method of claim 20 , wherein the executing the external linkage information occurs after the executing the body code section.

23. The method of claim 20 , wherein the executing of the external linkage information overlaps the executing the body code section.

24. An apparatus for compiling a cycle-based logic design, comprising:

means for inputting a plurality of modules of the cycle-based logic design and an input file into a plurality of compilers, wherein each of the plurality of modules describes a combinational logic component of the cycle-based logic design having an input port and an output port;

means for compiling separately the plurality of modules to generate a plurality of object files, wherein at least one of the plurality of object files comprises a body code section and an external linkage information section; and

means for linking the plurality of object files into an executable file for simulating the cycle-based logic design, wherein the executable file is stored as a data structure defined for a massively parallel processor environment.