Derating factor determination for integrated circuit logic design tools
View Patent ↗An integrated circuit development library is provided that characterizes several different logic device cells. The library specifies a number of different timing relationships for each of the logic device cells. These timing relationships are evaluated for each of the logic device cells at a first derating condition with a first simulator to provide a first set of derated condition values. The first set of derated condition values each correspond to one of the timing relationships evaluated. A first derating factor is calculated from the first set of derated condition values for estimating derated performance of an integrated circuit with a second simulator. This integrated circuit is developed from one or more of the logic device cells of the library.
1. A method, comprising:
(a) providing an integrated circuit development library characterizing several different logic device cells, the library specifying a number of different timing relationships for each of the logic device cells;
(b) determining a number of derating values for characterizing derated performance of each of the logic device cells, each of the derating values being determined by evaluating a different one of the timing relationships for each of the logic device cell descriptions at a derating condition with a first simulator; and
(c) calculating a number of derating factors, the derating factors each being determined from a different subset of the derated condition values, the derating factors being applicable to estimate derated performance of an integrated circuit developed from the library with a second simulator, the calculating of the number of derating factors including:
establishing a number of best cast multiplier arrays and a number of worst case multiplier arrays; and
screening each of the best case multiplier arrays and each of the worst case multiplier arrays.
2. The method of claim 1 , wherein the derating condition corresponds to one of temperature, voltage, or process.
3. The method of claim 1 , further comprising evaluating each of the timing relationships for each of the logic device cells at a different derating condition with the first simulator to provide other derated condition values.
4. An apparatus, comprising: a processing system including:
means for providing a library including a plurality of logic device cell descriptions each including a number of timing relationships;
means for determining a number of derating values for characterizing derated performance of each of the logic device cells, each of the derating values being determined by evaluating a different one of the timing relationships for each of the logic device cell descriptions at a derating condition with a first simulator; and
means for calculating a number of derating factors, the derating factors each being determined from a different subset of the derating values, the derating factors being applicable to estimate derated performance of an integrated circuit developed from the library with a second simulator, and wherein said calculating means includes means for establishing a number of best case multiplier arrays and a number of worst case multiplier arrays and means for screening each of the best case multiplier arrays and each of the worst case multiplier arrays.
5. The apparatus of claim 4 , wherein said providing means includes a computer readable medium encoded with said library.
6. The apparatus of claim 4 , wherein said calculating means includes a processor operable to execute a derating factor extraction program to calculate said derating factors.