Software input/output using hard real time threads
View Patent ↗A system and method for implementing high speed input and output protocols in software using hard real time threads. The processor provides both high speed and deterministic performance. The hard real time threads execute enough instructions per clock cycle of the input and output protocol to regularly transfer data.
1. A method for implementing a high speed input and output protocol in software as a hard real time thread on a multithreaded processor, comprising the steps of:
scheduling instructions of the hard real time thread of the high speed input and output protocol to be executed as a predetermined fraction of all scheduled instructions on the multithreaded processor over a first time period;
generating a schedule allocating cycles of an input and output protocol clock signal to a plurality of threads so instructions of the hard real time thread execute during cycles of the input and output protocol clock signal specified by the schedule;
generating the input and output protocol clock signal, a selected number of the instructions of the hard real time thread being executed each cycle of the input and output protocol clock signal, each instruction of the selected number of instructions being executed at the same time for each cycle of the input and output protocol clock signal; and
executing a first predetermined instruction of the selected number of the instructions at a first predetermined time within the cycle of the input and output protocol clock signal to transfer data.
2. The method of claim 1 , wherein the execution of the first predetermined instruction of the selected number of the instructions transmits data and further comprising executing a second predetermined instruction of the selected number of instructions at a second predetermined time within the cycle of the clock to receive data.
3. The method of claim 1 , wherein the high speed input and output protocol implemented in software has a data transfer speed greater than 200 kbps.
4. The method of claim 1 , wherein the high speed input and output protocol implemented in software has a data transfer speed of at least approximately 8 Mbps.
5. The method of claim 1 , wherein the high speed input and output protocol implemented in software has a data transfer speed of at least approximately 100 Mbps.
6. The method of claim 1 , wherein the input and output protocol clock signal is generated with hardware.
7. The method of claim 1 , further comprising the step of executing instructions to perform only one of transmitting data and receiving data in a single input and output protocol clock cycle.
8. The method of claim 1 , wherein the selected number of instructions are sufficient to perform only one of transmitting data and receiving data in each of a plurality of consecutive input and output protocol clock cycles.
9. The method of claim 1 , wherein the selected number of instructions are sufficient to perform only one of transmitting data and receiving data in every other of a plurality of consecutive input and output protocol clock cycles.
10. The method of claim 1 , further comprising synchronizing the selected number of instructions to the generated clock so that execution of an instruction in the first half of the selected number of instructions operates to receive data, and execution of an instruction in the second half of the selected number of instructions operates to transmit data.
11. The method of claim 1 , wherein the selected number of instructions are six.
12. The method of claim 1 , further comprising:
receiving a request for the input and output protocol;
in response to receiving the request, executing instructions of the hard real time thread to wake the software implementation of the input and output protocol from suspension; and
in response to completing transfer of data, executing instructions to suspend the software implementation of the input and output protocol.
13. The method of claim 1 , wherein the multithreaded processor comprises a memory to memory instruction set.
14. The method of claim 1 , wherein the multithreaded processor comprises a nonstalling instruction pipeline.
15. The method of claim 1 , wherein the multithreaded processor comprises an on chip memory that stores the operating system for the processor.
16. The method of claim 1 , wherein the clock signal is generated by execution of at least one instruction of the selected number of the instructions.
17. The method of claim 1 , further comprising the steps of:
executing instructions to transmit data while the generated input and output protocol clock signal is at a first level; and
executing instructions to receive data while the generated input and output protocol clock is at a second level.
18. The method of claim 17 , further comprising the step of executing instructions to transmit and receive data in a single complete input and output protocol clock cycle.
19. The method of claim 17 , wherein the selected number of instructions are sufficient to transmit and receive data during each of a plurality of consecutive input and output protocol clock cycles.
20. A method for implementing a high speed input and output protocol in software as a hard real time thread on a multithreaded processor, comprising the steps of:
scheduling instructions of the hard real time thread of the high speed input and output protocol to be executed as a predetermined fraction of all scheduled instructions on the multithreaded processor over a first time period;
generating an input and output protocol clock signal, a selected number of the instructions of the hard real time thread being executed each cycle of the input and output protocol clock signal, each instruction of the selected number of instructions being executed at the same time for each cycle of the input and output protocol clock signal;
executing a first predetermined instruction of the selected number of the instructions at a first predetermined time within the cycle of the input and output protocol clock signal to transfer data;
executing instructions to transmit data while the generated input and output protocol clock signal is at a first level; and
executing instructions to receive data while the generated input and output protocol clock is at a second level,
wherein the instructions to transmit data comprises a plurality of subsets of transmit instructions and the instructions to receive data comprises a plurality of subsets of receive instructions.
21. The method of claim 20 , further comprising the steps of:
executing instructions of a first subset of transmit instructions to transmit data while the generated input and output protocol clock is in one state;
executing instructions of the first subset of transmit instructions to determine which subset of transmit instructions to execute during the next generated input and output protocol clock cycle;
executing at least one instruction of the first subset of transmit instructions to switch to a first subset of receive instructions; and
executing the first subset of receive instructions, including at least one instruction to switch to the determined subset of transmit instructions.
22. The method of claim 20 , wherein each of the plurality of subsets of transmit instructions includes at least one instruction indicating which of the plurality of subsets of receive instructions to execute the next time the generated input and output protocol clock is at the second level.
23. The method of claim 20 , wherein each of the plurality of subsets of receive instructions includes at least one instruction indicating which of the plurality of subsets of transmit instructions to execute the next time the generated input and output protocol clock is at the first level.