Lateral DMOS transistor having reduced surface field
View Patent ↗In accordance with the present invention, a metal oxide semiconductor (MOS) transistor has a substrate of a first conductivity type. A drift region of a second conductivity type is formed over the substrate. A body region of the first conductivity type is formed in the drift region. A source region of the second conductivity is formed in the body region. A gate extends over a surface portion of the body region and overlaps each of the source region and the body region such that the surface portion of the body region forms a channel region of the transistor. A drain region of the second conductivity type is formed in the drift region. The drain region is laterally spaced from the source region a first predetermined distance. A first buried layer of the first conductivity type extends into the substrate and the drift region. The first buried layer laterally extends between the source and drain regions.
1. A metal oxide semiconductor (MOS) transistor comprising:
a substrate of a first conductivity type;
a drift region of a second conductivity type over the substrate;
a body region of the first conductivity type in the drift region;
a source region of the second conductivity in the body region;
a gate extending over a surface portion of the body region and overlapping each of the source region and the drift region such that the surface portion of the body region forms a channel region of the transistor;
a drain region of the second conductivity type in the drift region, the drain region being laterally spaced from the source region a first predetermined distance; and
a first buried layer of the first conductivity type extending into the substrate and the drift region, the first buried layer laterally extending between the source and drain regions and having a laterally non-uniform impurity density.
2. The MOS transistor of claim 1 wherein the impurity density of the first buried layer is higher along its source side than along its drain side.
3. The MOS transistor of claim 1 wherein the impurity density of the first buried layer dercases from its source side to its drain side.
4. The MOS transistor of claim 1 further comprising a second buried layer of the first conductivity type extending into the substrate and the drift region, the second buried layer being directly below the source region adjacent the first buried layer.
5. The MOS transistor of claim 4 wherein the impurity density of the first buried layer is highest near the second buried layer and decreases in a direction away from the second buried layer.
6. The MOS transistor of claim 4 further comprising a well region of the second conductivity type in the drift region, the well region separating but being in contact with the body region and the second buried layer.
7. The MOS transistor of claim 1 further comprising a third buried layer of the second conductivity type extending into the substrate and the drift region directly below the drain region.
8. The MOS transistor of claim 7 wherein the first and third buried layers are laterally spaced apart from one anther.
9. The MOS transistor of claim 1 wherein the first buried layer is made up of a plurality of contiguous regions each having a different impurity density.
10. The MOS transistor of claim 1 further comprising:
a drain electrode contacting the drain region;
a source electrode contacting the source region; and
an interlayer dielectric layer electrically isolating the gate, the source electrode, and the drain electrode from one another.
11. The MOS transistor of claim 1 wherein the first conductivity type is p-type and the second conductivity type is n-type.
12. The MOS transistor of claim 1 wherein the first buried layer laterally extends a distance greater than one-half of the first predetermined distance.
13. The MOS transistor of claim 1 wherein the first buried layer laterally extends from below the body region to a predetermined location between the body and drain regions.