Apparatus and method for snoop access in a dual access, banked and pipelined data cache memory unit
View Patent ↗In a data cache unit that exchanges data signal groups with at least two execution units, the operation of the data cache unit is implemented as a three-stage pipeline in order to access data at the speed of the system clock. The data cache unit has a plurality of storage cell banks. Each storage cell bank has valid bit array unit and a tag unit for each execution unit incorporated therein. Each valid bit array unit has a valid/invalid storage cell associated with each data group stored in the storage cell bank. The valid bit array units have a read/write address port and snoop address port. During a read operation, the associated valid/invalid signal is retrieved to determine whether the data signal group should be processed by the associated execution unit. In a write operation, a valid bit is set in the valid/invalid bit location(s) associated with the storage of a data signal group (or groups) during memory access. The valid bit array unit responds to a snoop address and a control signal from the tag unit to set an invalid bit in a valid/invalid bit address location associated with the snoop address. The tag unit can be divided into a plurality of tag subunits to expedite processing.
1. In a data cache memory interacting with a first execution unit and a second execution unit; a valid bit array unit, the unit comprising:
a group of addressable storage cells, the data cache memory including a tag unit, each storagc cell storing a valid/invalid bit signal;
a first address port for accessing a plurality of storage cells during a read and a write operation in response to an address signal group, the valid bit array unit retrieving a plurality of valid bit signals from the accessed location in response to read operation address signal group, the valid bit array unit storing a valid bit;
a second address port for accessing a plurality of storage cell location in response to a snoop address signal group;
a control signal port having a control signal generated from the from the tag unit applied thereto, wherein the application of the control signal specifies the storage cell of the valid bit to be changed to an invalid bit; and wherein
the tag unit is divided into a first plurality of independently addressable subunits, wherein application of an address signal group to the address port in a read operation causes the retrieval of the plurality of signals in valid/invalid bit locations associated with each tag subunit; and,
the valid bit array unit is located between the tag subunits to minimize difference in transit time between signals of the tag subunits.
2. The valid bit array unit as recited in claim 1 further comprising:
a second control signal port, wherein application of a second control signal indicative of the storage of a plurality of data signal groups in the data cache memory unit and an address signal group applied to the address port causes the storage of a plurality of valid signals at locations in the valid bit array unit corresponding to the location of the data signal groups.
3. The valid bit array unit as recited in claim 1 wherein the valid bit array unit further comprises:
a multiplexer coupled to output terminals of valid bit array unit, the multiplexer selecting the plurality of valid/invalid bit locations corresponding to one tag subunit for transmission.
4. The valid bit array unit of claim 1 wherein an access to the data cache unit takes at most three system clock cycles, the snoop operation taking two system clock cycles.
5. The valid bit array unit of claim 4 wherein the generation of a control signal by the tag unit is implemented in one clock cycle and the setting of an invalid bit at a location in valid bit array unit is implemented in a second system clock cycle.
6. The valid bit array unit of claim 1 , wherein the data cache unit is divided into a plurality of storage cell banks, each storage cell bank having a least one valid bit array unit incorporated therein.