Feed-forward amplifier loop control utilizing if signal processing
View Patent ↗An amplifier arrangement including a main amplifier to which feed-forward cancellation is applied, where the amplifier arrangement comprises an input for receiving signals to be amplified, an output for providing an amplified input signal, a pilot signal modulation circuit to generate a CW frequency shifted pilot signal, a mixer down for converting the pilot signal to an IF signal, and a sampling circuit for digitally sampling the IF signal. The amplifier arrangement includes a signal cancellation loop and a distortion cancellation loop each acting as an independent control function for minimizing pilot signal. The signal cancellation loop utilizes a Cartesian loop method for controlling the signal cancellation loop for sensing both phase and amplitude information simultaneously. The Cartesian loop uses a high frequency active mixer, which is a dual cross coupled differential pairs of devices capable of operating with input signals from near DC to 2.4 GHz, for control of the signal cancellation loop.
1. An amplifier arrangement including an input for receiving signals to be amplified, an output for providing an amplified input signal, and a main amplifier to which feed-forward cancellation is applied, the amplifier arrangement comprising:
a signal modulation circuit for generating a CW frequency shifted pilot signal;
a mixer down for converting the pilot signal to an IF signal;
a digital signal processor circuit for digitally sampling the IF signal.
2. The amplifier arrangement defined in claim 1 , wherein the pilot signal is frequency shifted by modulation of a base band signal by a pilot reference signal.
3. The amplifier arrangement defined in claim 1 , wherein I and Q information for the IF signal are extracted by digital sampling of the IF signal.
4. The amplifier arrangement defined in claim 1 , wherein amplitude and phase information for the IF signal are extracted by digital sampling of the IF signal.
5. The amplifier arrangement defined in claim 3 , wherein the I and Q information are applied to I and Q controllers to adjust magnitude and phase of error path to be identical to magnitude and phase of main delay path line.
6. The amplifier arrangement defined in claim 4 , wherein the I and Q information are applied to I and Q controllers to adjust I and Q of error path to be identical to I and Q of main delay path line.
7. The amplifier arrangement defined in claim 1 , wherein the sampling is performed by CMOS analog switches.
8. The amplifier arrangement defined in claim 1 , wherein the sampling is performed digitally by digital switches or gates.
9. The amplifier arrangement defined in claim 8 , wherein the sampling is performed digitally by an FPGA chip.
10. The amplifier arrangement defined in claim 1 , wherein the pilot signal is injected in a middle stage of the main amplifier chain.
11. The amplifier arrangement defined in claim 10 , wherein the injection is at 30 to 50 dB below desired system signal level.
12. The amplifier arrangement defined in claim 1 , further comprising an attenuator for attenuating output signal in order to prevent it from over-driving down converter mixer that produces the IF signal.
13. The amplifier arrangement defined in claim 1 , wherein a continuous 360-degree phase adjustment between the sampling signals and the base-band signals is performed in order to allow adjusting of the timing signals so that samplers extract the proper phase and amplitude information for phase and amplitude loop lock.
14. The amplifier arrangement defined in claim 13 , wherein calibration is accomplished without requiring manual, voltage controlled RF frequency phase shifters or trimming of cable lengths.
15. The amplifier arrangement defined in claim 1 , wherein error and main amplifiers are shut down upon loss of lock of signal cancellation loop.
16. The amplifier arrangement defined in claim 1 , wherein the error amplifier is shut down upon loss of lock of distortion cancellation loop.
17. The amplifier arrangement defined in claim 16 , wherein an auto calibration is performed as a corrective remedy to bring the distortion cancellation loop back into lock.
18. The amplifier arrangement defined in claim 1 , wherein auto calibration is performed on a periodic basis.
19. The amplifier arrangement defined in claim 1 , wherein the auto calibration is performed upon power up.
20. The amplifier arrangement defined in claim 1 , wherein auto calibration is performed during factory alignment and testing.
21. An amplifier arrangement including a main amplifier to which feed-forward cancellation is applied, said amplifier arrangement comprising:
a signal cancellation loop and a distortion cancellation loop each acting as an independent control function for minimizing pilot signal;
the signal cancellation loop utilizing the Cartesian loop method for controlling the signal cancellation loop for sensing both phase and amplitude information simultaneously;
the Cartesian loop utilizing a high frequency linear mixer for control of the signal cancellation loop.
22. The amplifier arrangement of claim 21 , wherein the high frequency active mixer is a dual cross coupled differential pairs of devices.
23. The amplifier arrangement of claim 21 , wherein use of the mixer results in substantial cancellation of DC drift signal.
24. The amplifier arrangement of claim 20 , wherein the mixer is capable of operating with input signals from near DC to 2.4 GHz.
25. The amplifier arrangement of claim 21 , wherein the mixer is a Motorola MC13143D multiplier.
26. The amplifier arrangement of claim 21 , wherein use of said linear multiplier results in an improvement of at least 10 dB in operating dynamic range over a diode method of signal mixing or detection.