Nonvolatile semiconductor memory device
View Patent ↗A nonvolatile semiconductor memory device includes a memory array which comprises a plurality of memory cells of a type wherein predetermined voltages are applied to selected memory cells to change their threshold voltages, whereby information are stored therein according to the difference between the threshold voltages, and whose some memory cells are used as spare memory cells. The nonvolatile semiconductor memory device is provided with a latch circuit connected to each bit line of the memory array through a transmission switch. The memory array is capable of storing therein at least substitutional information for replacing a defective bit by the spare memory cell. The substitutional information is transferred from the memory array to the latch circuit through the transmission switch and held in the latch circuit.
1. A nonvolatile memory comprising:
a nonvolatile memory array comprising a first area and a second area; and
a control circuit,
wherein said nonvolatile memory array includes a plurality of memory cells each of which belongs one of said first area or said second area,
wherein said control circuit performs programming and reading in said first area,
wherein in said programming, said control circuit is adapted to store same data within first memory cells in said first area and within second memory cells in said first area,
wherein storing of said same data within said first memory cells is carried out before storing of said same data within said second memory cells, and
wherein in said reading, said controller circuit is adapted to read said same data from said first memory cells and from said second memory cells at once.
2. A nonvolatile memory according to claim 1 ,
wherein said memory array includes a first address decoder and a second address decoder,
wherein said first address decoder decodes an address for accessing said first memory area, and
wherein said second address decoder decodes an address received from outside of said nonvolatile memory for accessing said second memory area.
3. A nonvolatile memory according to claim 2 , wherein said address for accessing said first memory area is generated in said nonvolatile memory.
4. A nonvolatile memory according to claim 1 ,
wherein said nonvolatile memory array includes a plurality of word lines each of which connects to corresponding ones of said memory cells, and
wherein a first of said plurality of word lines connects to said first memory cells and a second of said plurality of word lines connects to said second memory cells.
5. A nonvolatile memory according to claim 4 , wherein said first area is arranged in said memory array closed at address terminals.
6. A nonvolatile memory according to claim 4 ,
wherein said programming to said first memory cells and said second memory cells is capable of being performed after packaging.
7. A nonvolatile memory according to claim 6 , wherein said data includes rescue data.
8. A nonvolatile memory according to claim 6 , wherein said data includes trimming data.