Network security protocol processor and method thereof
A cryptographic processor having an in-line (i.e., “bump-in-the-wire”) architecture processes data packets between a trusted domain and a untrusted domain, according to a predetermined security protocol. The cryptographic processor can be implemented as a stand-alone device, without requiring a change in the configuration of the host machine. Unlike a conventional hardware acceleration of a “bump-in-the-stack” implementation, which is typically implemented as a layer between the native IP layer and the network drivers in an IP protocol stack and uses a single bus interface (e.g., a PCI-X bus) for all data traffic, the cryptographic processor acts as a security gateway, providing separate interfaces for the trusted and the untrusted domains. The cryptographic processor includes pipeline stages for carrying a feedback encryption algorithm with optimal throughput.
1. An apparatus for in-line processing data packets according to a network security protocol, comprising:
a first network interface to a first computer network;
a second network interface to a second computer network;
a first data path, coupled to receive the data packets from the first network interface, the first data path comprising:
a first group of pipeline stages for encrypting the data packets, using a feedback encryption algorithm;
a first packet building circuit that encapsulates the encrypted data packets with security data bits of the security protocol and transmits the encapsulated data packets over the second network interface; and
a first security policy lookup circuit for identifying one or more applicable security policies under the network security protocol applicable to each data packet;
a second data path, coupled to receive encrypted data packets that are encapsulated according to the network security protocol, the second data path comprising:
an integrity verification circuit that examines the security data bits to determine integrity of each encrypted data packet;
a second group of pipeline stages for decrypting the encrypted data packets;
a second packet building circuit that transmits the decrypted data packets over the first network interface; and
a second security policy lookup circuit for identifying one or more applicable security policies under the network security protocol applicable to each data packet.
2. An apparatus as in claim 1 , wherein the first group of pipeline stages comprises:
a receiving stage providing storage for the data packets to be encrypted;
a plurality of buffers each receiving a data packet at a time from the receiving stage;
a multiplexer coupled to the buffers, the multiplexer removing at each clock period a predetermined number of data bits from a different one of the data packets in the buffers according to a predetermined schedule; and
a plurality of pipeline stages for performing the feedback encryption algorithm on each of the predetermined number of data bits removed by the multiplexer.
3. An apparatus as in claim 2 , wherein the number of pipeline stages for performing the feedback encryption algorithm is not greater than the number of buffers.
4. An apparatus as in claim 1 , wherein the security lookup circuit includes a cache memory for storing valid security policies.
5. An apparatus as in claim 4 , wherein the cache memory comprises content addressable memories.
6. An apparatus as in claim 5 , wherein the cache memory comprises a memory array, a comparator and a control circuit, and wherein the entries stored in the memory array are sorted, and the control circuit implements a binary search algorithm for searching the memory array using a key entry to be matched.
7. An apparatus as in claim 1 , further comprising in each of the first and second data paths a security association lookup circuit for identifying one or more applicable security associations under the network security protocol applicable to each data packet.
8. An apparatus as in claim 7 , wherein the security association lookup circuit includes a cache memory for storing valid security associations.
9. An apparatus as in claim 7 , wherein the cache memory comprises content addressable memories.
10. An apparatus as in claim 7 , wherein the cache memory comprises a memory array, a comparator and a control circuit, and wherein the entries stored in the memory array are sorted, and the control circuit implements a binary search algorithm for searching the memory array using a key entry to be matched.
11. An apparatus as in claim 1 , further comprising a key exchange circuit including a state machine for carrying out a key exchange algorithm under the network security protocol.
12. An apparatus as in claim 1 , wherein the feedback encryption algorithm comprises a cipher block chaining mode encryption algorithm.
13. An apparatus as in claim 1 , wherein the apparatus is implemented in an integrated circuit.
14. A method for in-line processing data packets according to a network security protocol, comprising:
providing a first network interface to a first computer network;
providing a second network interface to a second computer network;
using a first pipelined data path to perform:
receiving data packets from the first network interface;
encrypting the data packets, using a feedback encryption algorithm;
encapsulating the encrypted data packets with the security data bits of the security protocol and transmitting the encapsulated data packets over the second network interface; and
identifying one or more applicable security policies under the network security protocol applicable to each data packet on a first security policy lookup circuit; and
using a second pipelined data path to perform:
receiving from the second network interface encrypted data packets that are encapsulated according to the network security protocol;
verifying the integrity of the encrypted data packets by examining the security data bits of each encrypted data packet;
decrypting the encrypted data packets;
transmitting the decrypted data packets over the first network interface; and
identifying one or more applicable security policies under the network security protocol applicable to each data packet on a second security policy lookup circuit.
15. A method as in claim 14 , wherein encrypting the data packets comprises:
storing data bits of each data packet to be encrypted until the entire packet is received;
storing each received data packet in one of a plurality of buffers;
removing at each clock period a predetermined number of data bits from a different one of the data packets in the buffers according to a predetermined schedule; and
performing the feedback encryption algorithm in a pipelined manner on each of the predetermined number of data bits removed.
16. A method as in claim 15 , further comprising providing a number of pipeline stages for performing the feedback encryption algorithm that is not greater than the number of buffers.
17. A method as in claim 14 , further comprising providing a cache memory for storing valid security policies to facilitate looking up the security policy.
18. A method as in claim 17 , wherein the cache memory comprises content addressable memories.
19. A method as in claim 18 , further comprising operating the cache memory by:
sorting data entries in a memory array; and
performing a binary search to determine if a key entry matches any of the stored data entries in the memory array.
20. A method as in claim 14 , further comprising in each of the first and second data paths looking up a security association to identify one or more applicable security associations under the network security protocol applicable to each data packet.
21. A method as in claim 20 , wherein looking up a security association is performed on valid security associations stored in a cache memory.
22. A method as in claim 20 , wherein the cache memory comprises content addressable memories.
23. A method as in claim 14 , further comprising carrying out a key exchange algorithm under the network security protocol to determine encryption keys for encrypting the data packets.
24. A method as in claim 14 , wherein the feedback encryption algorithm comprises a cipher block chaining mode encryption algorithm.
25. A method as in claim 14 , wherein the method is carried out in an integrated circuit.