Control module comprising a ROM with reduced electrical consumption

1. A control module, comprising the following elements:

a read-only memory (ROM),

a temporary buffer, into which the data of said ROM can be transferred in order to be accessible from outside the control module,

a read controller, for selecting at each cycle portions of said ROM transferred into said temporary buffer, the selected portions depending on the contents of said ROM,

wherein said ROM comprises one or more bits indicating a portion of said ROM, said one or more bits allowing said read controller to be controlled so that said portion is not selected to be transferred into said temporary buffer.

2. The control module of claim 1 , comprising a column preload circuit of said ROM, the columns preloaded at each reading cycle being dependent on the contents of said ROM.

3. The control module of claim 2 , wherein only the columns corresponding to said portions selected by said read controller are preloaded.

4. The control module of claim 1 , comprising a circuit for reading the columns of said ROM, said reading circuit including sense amplifiers, the sense amplifiers activated at each reading cycle for reading the columns being dependent on the contents of said ROM.

5. The control module of claim 4 , wherein each line of said ROM is divided in several sections,

said read controller selecting according to the contents of said ROM the sections of the selected line transferred into said temporary buffer at each reading cycle.

6. The control module of claim 5 , wherein at least certain lines of said ROM contain at least one bit indicating the sections transferred into said temporary buffer during at least one subsequent reading cycle.

7. The control module of claim 6 , wherein each line of said ROM contains at least one bit indicating the sections transferred into said temporary buffer during the next reading cycle.

8. The control module of claim 7 , wherein said ROM drains more current for reading one bit having a first logic level than for reading one bit having a second logic level,

and wherein the bits indicating that a section is to be transferred are encoded with said second logic level.

9. The control module of claim 1 , wherein said temporary buffer is constituted by an instructions register.

10. The control module of claim 5 , wherein said ROM drains more current for reading one bit having a first logic level than for reading one bit having a second logic level, and wherein the concentration of bits having said first logic level is lower in the sections that are not to be transferred into said temporary buffer.

11. The control module of claim 1 , wherein said ROM drains more current for reading one bit having a first logic level than for reading one bit having a second logic level,

and wherein said non-selected portion of said ROM is encoded with bits having the second logic level.

12. The control module of claim 1 , wherein the columns of said ROM are divided in several groups, a plurality of multiplexers allowing to select at each reading cycle a column in each group of columns, only the selected columns being preloaded and read during said cycle.

13. The control module of claim 12 , wherein said read controller determines at each cycle which of the signals at the output of said multiplexers are transferred into an element of said temporary buffer.

14. A signal processor comprising at least one control module according to claim 1 .

15. An hearing-aid device comprising at least one signal processor according to claim 14 .