IP Library Granted Patent US 7,162,403
Granted Patent B2
US 7,162,403 · App. 10/366,859 · Granted Jan 9, 2007

System and method for efficiently tracing simulation data in hardware acceleration simulation systems

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,162,403
App. No.
10/366,859
Granted
Jan 9, 2007
Kind
B2
Abstract

A system for tracing signals for a cycle-based simulation includes a traced signal and a system resources availability information of the cycle-based simulation, a runtime compiler configured to use the system resources availability information to assign a system resource to trace the traced signal, a logic design used with the system resources availability information to generate a simulation image, a first value of the traced signal generated by execution of a simulation image, and a traced signal buffer configured to store the first value and upload the first value.

Claims (69)

1. A system for tracing signals in a cycle-based simulation, comprising:

a plurality of resources comprising at least one selected from a group consisting of an execution processor and a routing processor;

a compiler configured to:

determine an availability of each of the plurality of resources during a cycle of the cycle-based simulation; and

generate a simulation image using the availability and a logic design;

a tracing information comprising a signal in the simulation image to be traced; and

a runtime compiler configured to:

generate a block of trace code using the tracing information; and

assign the block of trace code to at least one of the plurality of resources to trace the signal, wherein the block of trace code is assigned based on the availability.

2. The system of claim 1 , further comprising:

a traced signal buffer configured to store a value generated by execution of the simulation image.

3. The system of claim 2 , wherein the value is generated during a first simulation cycle.

4. The system of claim 3 , wherein the traced signal buffer is configured to store the value during the first simulation cycle and during a second simulation cycle before uploading the value.

5. The system of claim 1 , wherein the simulation image is an object file.

6. The system of claim 1 , wherein the tracing information is generated using at least one selected from a group consisting of a static instruction-based approach, a dynamic instruction-based approach, a static table-driven approach, and a dynamic table-driven approach.

7. A method of tracing signals for a cycle-based simulation, comprising:

determining an availability of a plurality of resources during a cycle of the cycle-based simulation;

generating a simulation image using the availability and a logic design;

obtaining a tracing information comprising a signal to be traced;

generating a block of trace code using the tracing information;

assigning the block of trace code to one of the plurality of resources based on the availability;

performing a first simulation cycle of the cycle-based simulation to generate a first value of the signal; and

tracing the signal using the first value and the one of the plurality of resources.

8. The method of claim 7 , wherein the tracing information is generated using at least one selected from a group consisting of a static instruction-based approach, a dynamic instruction-based approach, a static table-driven approach, and a dynamic table-driven approach.

9. The method of claim 7 , further comprising:

storing the first value in a traced signal buffer; and

advancing to a second simulation cycle of the cycle-based simulation.

10. The method of claim 9 , further comprising:

performing the second simulation cycle to generate a second value of the signal;

storing the second value in the traced signal buffer; and

uploading the first value and the second value from the signal buffer, wherein the advancing to the second simulation cycle occurs before the first value is uploaded.

11. The method of claim 10 , wherein the first value and the second value are uploaded when the traced signal buffer is full.

12. The method of claim 7 , wherein the one of the plurality of resources is an execution processor.

13. The method of claim 12 , further comprising:

inserting a synchronization instruction into an instruction sequence of the execution processor; and

inserting a loop back instruction into the instruction sequence.

14. A computer system for tracing signals in a cycle-based simulation, comprising:

a processor;

a memory;

a storage device; and

software instructions stored in the memory for enabling the computer system to:

determine an availability of a plurality of resources during a cycle of the cycle-based simulation;

generate a simulation image using the availability and a logic design;

obtain a tracing information comprising a signal to be traced;

generate a block of trace code using the tracing information;

assign the block of trace code to one of the plurality of resources based on the availability;

perform a first simulation cycle of the cycle-based simulation to generate a first value of the signal; and

trace the signal using the first value and the one of the plurality of resources.

15. The computer system of claim 14 , wherein the tracing information is generated using a least one selected from a group consisting of a static instruction-based approach, a dynamic instruction-based approach, a static table-driven approach, and a dynamic table-driven approach.

16. The computer system of claim 14 , further comprising software instructions to:

store the first value in a traced signal buffer; and

advance to a second simulation cycle of the cycle-based simulation.

17. The computer system of claim 16 , further comprising software instructions to:

perform the second simulation cycle to generate a second value of the traced signal;

store the second value in the traced signal buffer; and

upload the first value and the second value from the traced signal buffer, wherein the advance to the second simulation cycle occurs before the first value is uploaded.

18. The computer system of claim 17 , wherein the first value and the second value are uploaded when the traced signal buffer is full.

19. The computer system of claim 14 , wherein the one of the plurality of resources is an execution processor.

20. The computer system of claim 19 , further comprising software instructions to:

insert a synchronization instruction into an instruction sequence of the execution processor; and

insert a loop back instruction into the instruction sequence.

21. An apparatus for tracing signals in a cycle-based simulation, comprising:

means for determining an availability of a plurality of resources during a cycle of the cycle-based simulation;

means for generating a simulation image using the availability and a logic design;

means for obtaining a tracing information comprising a signal to be traced;

means for generating a block of trace code using the tracing information;

means for assigning the block of trace code to one of the plurality of resources based on the availability;

means for performing a first simulation cycle of the cycle-based simulation to generate a first value of the signal; and

means for tracing the signal using the first value and the one of the plurality of resources.

Assignments (2)
MERGER AND CHANGE OF NAME Recorded Dec 16, 2015
From: ORACLE USA, INC.; SUN MICROSYSTEMS, INC.; ORACLE AMERICA, INC.
To: ORACLE AMERICA, INC.
Reel/Frame 037302/0683 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2003
From: NOURI, NASSER; WU, PING-CHIH; SOUFI, MOHAMED; ALLISON, DAVID S.
To: SUN MICROSYSTEMS, INC.
Reel/Frame 013784/0855 →