Optimized high bandwidth cache coherence mechanism
View Patent ↗A method and apparatus for a coherence mechanism that supports a distributed memory programming model in which processors each maintain their own memory area, and communicate data between them. A hierarchical programming model is supported, which uses distributed memory semantics on top of shared memory nodes. Coherence is maintained globally, but caching is restricted to a local region of the machine (a “node” or “caching domain”). A directory cache is held in an on-chip cache and is multi-banked, allowing very high transaction throughput. Directory associativity allows the directory cache to map contents of all caches concurrently. References off node are converted to non-allocating references, allowing the same access mechanism (a regular load or store) to be used for both for intra-node and extra-node references. Stores (Puts) to remote caches automatically update the caches instead of invalidating the caches, allowing producer/consumer data sharing to occur through cache instead of through main memory.
1. A method for performing a coherence protocol in a shared-memory multiprocessor employing a directory-based cache coherence mechanism, comprising:
when a current cache-line state is noncached, transitioning to an exclusive clean state when a read to a line is performed by a processor;
when the current cache-line state is exclusive-clean at a second processor, transitioning to a shared state when the read to the line is performed by the processor;
when the current cache-line state is dirty at the second processor, transitioning to the exclusive-clean state when the read to the line is performed by the processor; and
when the current cache-line state is shared, remaining in the shared state when the read to the line is performed by the processor.
2. The method of claim 1 , further comprising:
processing a shared hint for read requests.
3. The method of claim 2 , wherein the processing further comprises:
when the current cache-line state is noncached, transitioning to the shared state when a read-shared-hint is requested by the processor;
when the current cache-line state is exclusive-clean at the second processor, transitioning to the shared state when the read-shared-hint is requested by the processor;
when the current cache-line state is dirty at the second processor, transitioning to the shared state when the read-shared-hint is requested by the processor; and
when the current cache-line state is shared, remaining in the shared state when the read-shared-hint is requested by the processor.
4. The method of claim 1 , further comprising:
processing a non-allocate read request;
processing a non-allocate write request; and
processing a read-modify-write atomic operation.
5. The method of claim 4 , wherein the processing the non-allocate read request further comprises:
when the current cache-line state is noncached, remaining in the noncached state when the non-allocate read to the line is performed by the processor;
when the current cache-line state is exclusive-clean at the second processor, remaining in the exclusive-clean state at the second processor when the non-allocate read to the line is performed by the processor;
when the current cache-line state is dirty at the second processor, remaining in the dirty state at the second processor when the non-allocate read to the line is performed by the processor; and
when the current cache-line state is shared, remaining in the shared state when the non-allocate read to the line is performed by the processor.
6. The method of claim 4 , wherein the processing the non-allocate write request further comprises:
when the current cache-line state is noncached, remaining in the noncached state when a non-allocate write to the line is requested by the processor;
when the current cache-line state is exclusive-clean at the second processor, transitioning to the dirty state at the second processor when the non-allocate write to the line is requested by the processor;
when the current cache-line state is dirty at the second processor, remaining in the dirty state at the second processor when the non-allocate write to the line is requested by the processor; and
when the current cache-line state is shared, transitioning to the noncached state when the non-allocate write to the line is requested by the processor.
7. The method of claim 4 , wherein the processing the read-modify-write atomic operation further comprises:
when the current cache-line state is noncached, remaining in the noncached state when the read-modify-write atomic operation to the line is requested by the processor;
when the current cache-line state is exclusive-clean at the second processor, transitioning to the noncached state when the read-modify-write atomic operation to the line is requested by the processor;
when the current cache-line state is dirty at the second processor, transitioning to the noncached state when the read-modify-write atomic operation to the line is requested by the processor; and
when the current cache-line state is shared, transitioning to the noncached state when the read-modify-write atomic operation to the line is requested by the processor.