Satellite set-top box decoder for simultaneously servicing multiple independent programs for display on independent display device

1. A satellite set-top box decoder apparatus formed on a single integrated circuit chip for simultaneously servicing a plurality of independent programs for display on independent display devices, comprising:

a first processor for demultiplexing multiple input transport streams to generate a first video stream corresponding to a first program, and to further generate a second video stream corresponding to a second program;

a Program Clock Recovery (PCR) circuit for extracting first PCR data from the transport streams corresponding to the first program, and for extracting second PCR data from the transport streams corresponding to the second program,

a clock circuit responsive to the first and second PCR data for generating a first clock signal that is synchronized to a program clock for the first program and for generating a second clock signal that is synchronized to a program clock for the second program, the clock circuit including a dual phase locked loop (PLL) circuit in which a first multiplexer selects one of a plurality of first control words provided from extracted first PCR data and in which a second multiplexer selects one of a plurality of second control words provided from extracted second PCR data to separately control outputs of the PLL, wherein the first clock signal and the second clock signal are synchronized to corresponding first and second programs, but not to each other, in order to have independently timed first and second clock signals;

a video decode circuit for simultaneously (1) decoding the first video stream under control of the first clock signal to render a signal, and (2) decoding second video stream under control of the second clock signal to render a second decoded video signal; and

a video converter for simultaneously converting the first and second decoded video signals into analog video form respectively based on first and second clock signals in order to produce simultaneously two independent video signals for display on first and second display devices, in which the first and second video signals are independently and simultaneously generated from the same integrated circuit chip.

2. The decoder apparatus of claim 1 , wherein the first processor demultiplexes the multiple input transport streams to generate a first audio stream corresponding to the first program, and a second audio stream corresponding to the second program; said apparatus further comprising:

an audio decode circuit for simultaneously decoding (1) the first audio stream under control of the first clock signal to generate a first audio output signal, and (2) second audio stream under control of the second clock signal to generate a second audio output signal; and

an audio converter for simultaneously converting the first and second audio output signals into PCM audio data for output, such that the first audio output signal is output simultaneously with the output of the first decoded video signal from the video converter, and the second audio output signal is output simultaneously with the output of the second decoded video signal from the video converter.

3. The decoder apparatus of claim 2 , wherein the audio decode circuit is an MPEG audio decoder.

4. The decoder apparatus of claim 2 , wherein the clock circuit comprises first and second external voltage controlled oscillators controlled by first and second Pulse Width Modulated (PWM) waveforms, where said first PWM waveform is derived from the first PCR data.

5. The decoder apparatus of claim 1 , wherein the video decode circuit is an MPEG-2/MPEG-1 compliant video decoder.

6. An integrated receiver circuit of a set-top box formed on a single integrated circuit chip for decoding and displaying first and second program signals, comprising:

a substrate of the integrated circuit chip providing a physical medium upon which the receiver circuit is constructed;

a first satellite receiver having its circuit elements disposed upon the substrate;

a second satellite receiver having its circuit elements disposed upon the substrate;

a data transport processor having its circuit elements disposed upon the substrate for parsing and demultiplexing multiple transport streams received from the first and second satellite receivers to generate a first audio-video signal and second audio-video signal, wherein said data transport processor further extracts a first Program Clock Recovery (PCR) value associated with the first audio-video signal and a second PCR value associated with the second audio-video signal;

a clock generator having its circuit elements disposed upon the substrate for synthesizing a first clock signal that is synchronized to the first program signal and a second clock signal that is synchronized to the second program signal, the clock generator including a dual phase locked loop (PLL) circuit in which a first multiplexer selects one of a plurality of first control words provided from extracted first PCR value and in which a second multiplexer selects one of a plurality of second control words provided from extracted second PCR value to separately control outputs of the PLL, wherein the first clock signal and the second clock signal are synchronized to corresponding first and second program signals, but not to each other, in order to have independently timed first and second clock signals;

an audio-video decode processor for decoding the first and second audio-video signals, such that the first audio-video signal is decoded under control of the first clock signal, and the second audio-video signal is decoded under control of the second clock signal respectively in order to produce simultaneously two independent audio-video signals for output on first and second display devices, in which the first and second audio-video signals are independently and simultaneously generated from the same integrated circuit chip.

7. The integrated receiver of claim 6 additionally comprising an graphics engine circuit having its circuit elements disposed upon the substrate, said graphics engine accepting first and second decoded MPEG video streams from said data transport processor to provide compositing of text and graphics with said first stream under control of the first clock signal, and to simultaneously provide compositing of text and graphics with said second stream under control of the second clock signal.

8. The integrated receiver of claim 6 additionally comprising a video encoder circuit having its circuit elements disposed upon the substrate, said video encoder circuit accepting a first decoded MPEG video stream in YCRCB ( 601 ) format and producing composite video under control of the first clock signal, and accepting a second decoded MPEG video stream in YCRCB ( 601 ) format and producing composite video under control of the second clock signal.

9. The integrated receiver of claim 6 wherein the substrate is silicon.

10. The integrated receiver of claim 6 wherein the substrate comprises devices fabricated according to standard CMOS processing. and displaying the first and second program signals.