Higher order sigma-delta analog-to-digital converter based on finite impulse response filter

1. A sigma-delta analog-to-digital converter (ADC) comprising:

an infinite impulse response (IIR) filter having no more than one analog amplifier and further having an order greater than one and operational to generate a plurality of output signals;

a digital filter operational to filter out up-converted frequency quantization noise associated with at least one IIR filter output signal and generate a low frequency feedback signal therefrom; and

no more than one summing node, wherein the single summing node operates to sum the plurality of output signals and the low frequency feedback signal;

wherein the IIR filter further comprises a plurality of delay elements operational to cause the IIR filter to have an order greater than two.

2. A sigma-delta analog-to-digital converter (ADC) comprising:

an infinite impulse response (IIR) filter having no more than one analog amplifier and further having an order greater than one and operational to generate a plurality of output signals;

a digital filter operational to filter out up-converted frequency quantization noise associated with at least one IIR filter output signal and generate a low frequency feedback signal therefrom; and

no more than one summing node, wherein the single summing node operates to sum the plurality of output signals and the low frequency feedback signal;

wherein the IIR filter is based on a finite impulse response (FIR) architecture.

3. A sigma-delta analog-to-digital converter (ADC) comprising:

an infinite impulse response (IIR) filter having no more than one analog amplifier and further having an order greater than one and operational to generate a plurality of output signals;

a digital filter operational to filter out up-converted frequency quantization noise associated with at least one IIR filter output signal and generate a low frequency feedback signal therefrom; and

no more than one summing node, wherein the signal summing node operates to sum the plurality of output signals and the low frequency feedback signal;

further comprising means for compressing the low frequency quantization noise and pushing the compressed low frequency quantization noise into a higher frequency range to generate the up-converted frequency quantization noise.

4. A sigma-delta analog-to-digital converter (ADC) comprising:

an infinite impulse response (IIR) filter having no more than one analog amplifier and further having an order greater than one and operational to generate a plurality of output signals;

a digital filter operational to filter out up-converted frequency quantization noise associated with at least one IIR filter output signal and generate a low frequency feedback signal therefrom; and

no more than one summing node, wherein the single summing node operates to sum the plurality of output signals and the low frequency feedback signal;

wherein the IIR filter further comprises a plurality of switched capacitors.

5. A method of analog-to-digital conversion, the method comprising the steps of:

providing a sigma-delta analog-to-digital converter (ADC) having no less than a second order infinite impulse response (IIR) filter and possessing no more than one analog amplifier; and

converting an analog input signal to a digital signal to achieve a level of functionality substantially identical to a conventional sigma-delta ADC having more than one analog amplifier in terms of noise and swings at the output of the associated analog integrators;

wherein the IIR filter comprises an architecture that is based on a finite impulse response (FIR) filter architecture.

6. A method of analog-to-digital conversion, the method comprising the steps of:

providing a sigma-delta analog-to-digital converter (ADC) having no less than a second order infinite impulse response (IIR) filter and possessing no more than one analog amplifier; and converting an analog input signal to a digital signal to achieve a level of functionality substantially identical to a conventional sigma-delta ADC having more than one analog amplifier in terms of noise and swings at the output of the associated analog integrators;

wherein the step of converting an analog input signal to a digital signal comprises the steps of:

compressing low frequency quantization noise;

pushing the compressed low frequency quantization noise into a higher frequency range; and

digitally filtering out the higher frequency quantization noise.

7. A method of analog-to-digital conversion, the method comprising the steps of:

providing a sigma-delta analog-to-digital converter (ADC) having no less than a second order infinite impulse response (IIR) filter and possessing no more than one analog amplifier; and

converting an analog input signal to a digital signal to achieve a level of functionality substantially identical to a conventional sigma-delta ADC having more than one analog amplifier in terms of noise and swings at the output of the associated analog integrators;

wherein the step of converting an analog input signal to a digital signal comprises the steps of:

up-converting frequency quantization noise associated with at least one IIR filter output signal;

digitally filtering the up-converted frequency quantization noise to remove any high frequency quantization noise and generating a low frequency feedback signal therefrom; and

summing at one summing node, a plurality of output signals associated with the at least one IIR filter and the low frequency feedback signal.