Microprocessor and operation mode switching method for the microprocessor
View Patent ↗A microprocessor capable of supplying a stable internal clock signal even at the time of mode switching. A clock supply control circuit is connected between a clock generator circuit (PLL) and synchronous circuits (integer unit, instruction cache, data cache). The clock supply control circuit includes a bus interface unit, OR gates, and first and second delay circuits. With this microprocessor, when operations of the synchronous circuits are to be started, the supply of the internal clock signal from the PLL to the synchronous circuits is started in a time-staggered manner in order of the integer unit, the instruction cache, and the data cache. This serves to suppress noise at the start of operation and to keep the PLL locked, and as a result, the supply of the internal clock signal can be stabilized even at the time of mode switching.
1. A microprocessor having an operation mode switching function, comprising:
a clock generator circuit for generating a clock signal;
a first synchronous circuit operative in synchronism with a first clock signal given thereto;
a second synchronous circuit operative in synchronism with a second clock signal given thereto;
a third synchronous circuit operative in synchronism with a third clock signal given thereto;
a sleep signal generating circuit that produces a sleep signal depending on the operation mode of the microprocessor;
a first delay circuit that delays the sleep signal for a first delay time, thereby producing a first delayed sleep signal;
a second delay circuit that delays the sleep signal for a second delay time greater than the first delay time, thereby producing a second delayed sleep signal;
a first gate disposed between the clock generator circuit and the first synchronous circuit and coupled to the sleep signal generating circuit to produce and control the first clock signal, the first gate suppressing the first clock signal when the sleep signal is active;
a second gate disposed between the clock generator circuit and the second synchronous circuit and coupled to the first delay circuit to produce and control the second clock signal, the second gate suppressing the second clock signal when the first delayed sleep signal is active; and
a third gate disposed between the clock generator and the third synchronous circuit and coupled to the second delay circuit to produce and control the third clock signal, the third gate suppressing the third clock signal when the second delayed sleep signal is active.
2. The microprocessor according to claim 1 , wherein said first and second delay circuits comprise a number of flip-flops corresponding to the first and second delay times, respectively.
3. The microprocessor according to claim 1 , wherein said first and second delay circuits comprise a number of latches corresponding to the first and second delay times, respectively.
4. The microprocessor according to claim 1 , wherein:
said first synchronous circuit includes an arithmetic circuit;
said second synchronous circuit includes an instruction cache; and
said third synchronous circuit includes a data cache.
5. The microprocessor according to claim 1 , wherein said clock generator circuit comprises a PLL (Phase Locked Loop) circuit.