1R1D R-RAM array with floating p-well

1. A method for fabricating a one-resistor/one-diode (1R1D) R-RAM array with a floating p-well, the method comprising:

forming an integrated circuit (IC) substrate;

forming an n-doped buried layer of silicon (buried n layer) overlying the substrate;

forming a p-doped well of silicon (p-well) overlying the buried n layer; and,

forming a 1R1D R-RAM array overlying the p-well.

2. The method of claim 1 further comprising:

forming n-doped silicon sidewalls overlying the buried n layer;

forming an n-doped well (n-well) of silicon from the combination of n-doped silicon sidewalls and the buried n layer; and,

wherein forming a p-doped well of silicon (p-well) overlying the buried n layer includes forming the p-well inside th n-well.

3. The method of claim 2 wherein forming a p-well includes forming a p-well with sidewalk; and,

the method further comprising:

forming an oxide insulator overlying the p-well sidewalk, between the n-well and the R-RAM array.

4. The method of claim 3 wherein forming a p-well includes forming a p-well with a top surface; and,

wherein forming a 1R1D R-RAM array overlying the p-well includes:

forming a bit lines overlying the p-well top surface;

forming b word lines overlying and orthogonal to the bit lines; and,

forming (b×a) one-resistor/one-diode (1R1) elements interposed between each bit line and each overlying word line.

5. The method of claim 4 wherein forming (b ×a) one-resistor/one-diode(1R1) elements interposed between each bit line and each overlying word line includes:

forming b, oxide insulated word line trenches overlying and orthogonal to the bit lines;

in each trench forming a layer of p-doped silicon overlying the bit lines;

forming a layer of bottom electrode (BE) overlying the p-doped layer; and,

forming a layer of memory resistor material overlying the bottom electrode; and,

wherein forming b word lines overlying and orthogonal to the bit lines includes forming the word lines overlying the memory resistor layers.

6. The method of claim 5 wherein forming a p-doped well of silicon (p-well) includes doping the p-well with a doping density in the range between 1×10 15 /cm 3 and 1×10 17 /cm 3 .

7. The method of claim 5 wherein forming an n-doped buried layer of silicon (n layer) overlying the substrate includes doping the n-well using a material selected from the group including phosphorous, at an energy of 500 KeV to 2 MeV, and arsenic, at an energy of 1 MeV to 5 MeV, with a doping density in the range between 1×10 16 /cm 3 and 1×10 17 /cm 3 .

8. The method of claim 5 wherein forming a bit lines overlying the p-well top surface includes forming a bit lines of n-doped silicon overlying the p-well top surface.

9. The method of claim 5 wherein forming b word lines overlying and orthogonal to the bit lines includes forming word lines of top electrode (TE).

10. The method of claim 5 wherein forming a layer of memory resistor material overlying the bottom electrode includes using a memory resistor material selected from the group including Pr 0.3 Ca 0.7 MnO 3 (PCMO), colossal magnetoresistance (CMR), and high temperature superconductivity (HTSC) materials.

11. The method of claim 5 wherein forming a layer of bottom electrode overlying the p-doped layer includes forming the bottom electrode from a material selected from the group including Pt, Ir, and Pt/TiN/Ti.

12. The method of claim 1 wherein forming a p-doped well of silicon (p-well) overlying the buried n layer includes forming a p-well with a thickness in the range of 0.2 to 0.8 microns.

13. A one-resistor/one-diode (1R1) R-RAM with a floating p-well, the R-RAM comprising:

an integrated circuit (IC) substrate;

an n-doped buried layer of silicon (buried n layer) overlying the substrate;

a p-doped well of silicon (p-well) overlying the buried n layer; and,

a 1R1D R-RAM array overlying and inside the p-well.

14. The R-RAM array of claim 13 further comprising:

n-doped silicon sidewalls overlying the buried n layer,

wherein the combination of the n-doped silicon sidewalls and the buried n layer forms an n-well; and,

wherein the p-well is formed inside the n-well.

15. The R-RAM array of claim 14 wherein the p-well has sidewalls; and,

the R-RAM further comprising:

an oxide insulator overlying the p-well sidewalls, between the n-well and the R-RAM array.

16. The R-RAM array of claim 15 wherein the p-well has a top surface; and,

wherein the 1R1D R-RAM array includes:

a bit lines overlying the p-well top surface;

b word lines overlying and orthogonal to the bit lines; and,

(b×a) one-resistor/one-diode (1R1) elements interposed between each bit line and each overlying word line.

17. The R-RAM array of claim 16 further comprising:

b oxide insulated word line trenches overlying and orthogonal to the bit lines;

wherein the 1R1D elements includes:

in each word line trench, a layer of p-doped silicon overlying the bit lines;

a layer of bottom electrode (BE) overlying the p-doped layer; and,

a layer of memory resistor material overlying the bottom; and,

wherein the b word lines overlie the memory resistor layers.

18. The R-RAM array of claim 17 wherein the p-well is doped with a doping density in the range between 1×10 15 /cm 3 and 1×10 17 /cm 3 .

19. The R-RAM array of claim 17 wherein the n-well is doped with a material selected from the group including phosphorous, at an energy of 500 KeV to 2 MeV, and arsenic, at an energy of 1 MeV to 5 MeV, with a doping density in the range between 1×10 16 /cm 3 and 1×10 17 /cm 3 .

20. The R-RAM array of claim 17 wherein the a bit lines are n-doped silicon.

21. The R-RAM array of claim 17 wherein the b word lines are top electrodes.

22. The R-RAM of claim 17 wherein the memory resistor material is selected from the group including Pr 0.3 Ca 0.7 MnO 3 (PCMO), colossal magnetoresistance (CMR), and high temperature superconductivity (HTSC) materials.

23. The R-RAM of claim 17 wherein the bottom electrode is a material selected from the group including Pt, Ir, and Pt/TiN/Ti.

24. The R-RAM of claim 13 wherein the p-doped well of silicon has a thickness in the range of 0.2 to 0.8 microns.

25. A method for fabricating a one-resistor/one-diode (1R1D) R-RAM array with a floating p-well, the method comprising

forming an integrated circuit (IC) substrate;

forming an n-doped buried layer of silicon (buried n layer) overlying the substrate;

forming n-doped silicon sidewalls overlying the buried n layer;

forming an n-doped well (n-well) of silicon from the combination of n-doped silicon sidewalls and the buried n layer;

forming a p-doped well of silicon (p-well), with sidewalls and a top surface, overlying the buried n layer, inside the n-well;

forming an oxide insulator overlying the p-well sidewalls; and,

forming a 1R1D R-RAM array overlying the p-well as follows;

forming a bit lines overlying the p-well top surface;

forming b word lines overlying and orthogonal to the bit lines; and,

forming (b×a) one-resistor/one-diode (1R1D) elements interposed between each bit line and each overlying word line.

26. A one-resistor/one-diode (1R1) R-RAM with a floating p-well, the R-RAM comprising:

an integrated circuit (IC) substrate;

an n-doped buried layer of silicon (buried n layer) overlying the substrate;

n-doped silicon sidewalls overlying the buried n layer, wherein the combination of the n-doped silicon sidewalls and the buried n layer forms an n-well;

a p-doped well of silicon (p-well), with sidewalls and a top surface, overlying the buried n layer, inside the n-well;

an oxide insulator overlying the p-well sidewalls; and,

a 1R1D R-RAM array overlying and inside the p-well, wherein the 1R1D R-RAM array includes:

a bit lines overlying the p-well top surface;

b word lines overlying and orthogonal to the bit lines; and,

(b×a) one-resistor/one-diode (1R1) elements interposed between each bit line and each overlying word line.