Data communication method and data communication device and semiconductor device
View Patent ↗The present invention provides a data communication method and a data communication device capable of performing high-speed data communication by using a parallel link and higher-speed data communication by reducing a timing skew. A data communication method includes: a step of encoding data of N bits (N being 2 or larger) to transmission data of M bits (M being 3 or larger) on a transmission side; a step of generating a transmission signal in which transition takes place in at least one level of any of the transmission data synchronously with a transmission clock and transmitting the transmission signal to a transmission line on the transmission side; a step of recognizing transition in the signal of M bits received via the transmission line and detecting the reception data of M bits synchronized with the transmission clock on a reception side; and a step of decoding the reception data of M bits to the data of N bits.
1. An apparatus comprising a semiconductor device, the semiconductor device including:
a first circuit which converts a first signal of N bits (N being 2 or larger) into a second signal of M bits (M being 3 or larger); and
a second circuit which receives said second signal and outputs a third signal of said M bits,
wherein M is larger than N,
wherein said third signal is a signal in which transition takes place in at least one level of a predetermined number of signals out of said third signals synchronously with a clock signal, said first and second circuits are formed on a first semiconductor chip,
wherein said third signal is output to the outside of said first semiconductor chip,
wherein said first circuit generates said second signal in which at least one bit out of M bits has a first binary logic value,
wherein said second circuit generates said third signal which shifts the level of said second signals having said first binary logic value out of said M-bit second signals synchronously with said clock signal and which maintains said second signals having a second binary logic value at the same level, and
wherein said second circuit generates said third signal in which the number of bits having said first logic value is two or more, and
the apparatus further comprises a second semiconductor device formed on a second semiconductor chip, said second semiconductor device including:
a plurality of first MOSFETs connected in parallel which receive said third signal of M bits, and each said first MOSFET having a conductance characteristic substantially equal to a first value;
a plurality of second MOSFETs connected in parallel, the number of second MOSFETs being M, M-1 of said second MOSFETs each having a conductance characteristic substantially equal to said first value, and a remaining second MOSFET has a conductance characteristic which is substantially equal to one half the first value; and
a circuit which detects a difference between a first current flowing in said first MOSFETs and a second current flowing in said second MOSFETs and generates a detection signal indicative of validity/invalidity of the third signal,
wherein a voltage corresponding to one of two levels of said third signal is supplied to gates of said first MOSFETs which correspond to the number of bits having said first binary logic value, and to the remaining second MOSFET, and
wherein a voltage corresponding to the other level of the third signal is supplied to the gates of any remaining first MOSFETs.
2. An apparatus comprising a semiconductor device, the semiconductor device including:
a first circuit which converts a first signal of N bits (N being 2 or larger) into a second signal of M bits (M being 3 or larger); and
a second circuit which receives said second signal and outputs a third signal of said M bits,
wherein M is larger than N,
wherein said third signal is a signal in which transition takes place in at least one level of a predetermined number of signals out of said third signals synchronously with a clock signal, said first and second circuits are formed on a first semiconductor chip,
wherein said third signal is output to the outside of said first semiconductor chip,
wherein said N bits are parallel bits,
wherein said M bits are parallel bits,
wherein said first circuit generates said second signal in which at least one bit out of M bits has a first binary logic value,
wherein said second circuit generates said third signal which shifts the level of said second signals having said first binary logic value out of said M-bit second signals synchronously with said clock signal and which maintains said second signals having a second binary logic value at the same level, and
wherein said second circuit generates said third signal in which the number of bits having said first logic value is two or more, and
the apparatus further comprises a second semiconductor device formed on a second semiconductor chip, said second semiconductor device including:
a plurality of first MOSFETs connected in parallel which receive said third signal of M bits, and each said first MOSFET having a conductance characteristic substantially equal to a first value;
a plurality of second MOSFETs connected in parallel, the number of second MOSFETs being M, M-1 of said second MOSFETs each having a conductance characteristic substantially equal to said first value, and a remaining second MOSFET has a conductance characteristic which is substantially equal to one half the first value; and
a circuit which detects a difference between a first current flowing in said first MOSFETs and a second current flowing in said second MOSFETs and generates a detection signal indicative of validity/invalidity of the third signal,
wherein a voltage corresponding to one of two levels of said third signal is supplied to gates of said first MOSFETs which correspond to the number of bits having said first binary logic value, and to the remaining second MOSFET, and
wherein a voltage corresponding to the other level of the third signal is supplied to the gates of any remaining first MOSFETs.