IP Library Granted Patent US 7,606,233
Granted Patent B2
US 7,606,233 · App. 10/379,332 · Granted Oct 20, 2009

Method for micro-controller and DSP based data communication within a transceiver

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Quick Facts
Patent No.
US 7,606,233
App. No.
10/379,332
Granted
Oct 20, 2009
Kind
B2
Abstract

The present invention provides a method for improved data communication and a transceiver employing the method. In one embodiment, the method includes generating data blocks to transmit to a second transceiver, generating identification data for the data blocks and identifying the data blocks transmitted to the second transceiver based on the identification data.

Claims (28)

1. A method for transmitting data, comprising:

generating data blocks of a data package in a first transceiver to transmit to a second transceiver, said first transceiver including a micro-controller coupled to a digital signal processor;

generating identification data in said first transceiver for said data blocks, wherein said generating said data blocks and said identification data is performed by said micro-controller;

sending said data blocks and said identification data from said micro-controller to said digital signal processor in advance of transmission of said data blocks;

storing said data blocks and said identification data in said digital signal processor until time for said transmitting;

transmitting said data blocks with said identification data in data frames to said second transceiver;

identifying a transmission status of said data blocks transmitted to said second transceiver based on receiving said identification data in return from said second transceiver;

transmitting acknowledgment signals with said identification data from said second transceiver to a receiving buffer of said first transceiver; and

providing said acknowledgment signals with said identification data to said micro-controller via said digital signal processor to indicate said transmission status of said data blocks,

wherein a number of data blocks sent to said digital signal processor from said micro-controller is based on a number of said acknowledgment signals received from said second transceiver.

2. The method according to claim 1 further comprising providing an interleaved communication between said micro-controller and said digital signal processor.

3. The method according to claim 1 further comprising generating and transmitting data blocks of multiple data packages and choosing said identification data to be indexes of said multiple data packages to be transmitted.

4. The method according to claim 1 wherein said transmitting is via a multi-slot network and is triggered by an Uplink State Flag from a base station that indicates which slot of said multi-slot network to use for said transmitting of said data blocks.

5. A transceiver capable of transmitting data blocks, comprising:

a micro-controller configured to generate data blocks to transmit to a second transceiver and generate identification data for said data blocks, wherein said identification data is an index of a list of said data blocks to be transmitted and each of said data blocks is transmitted with said index;

a digital signal processor configured to receive said data blocks from said micro-controller, store said data blocks until time for said transmit and determine said time for said transmit based on a received message, said digital signal processor further configured to provide, to said micro-controller, said identification data that has been returned from said second transceiver after being transmitted thereto with said data blocks, said micro-controller further configured to employ said returned identification data to determine which of said data blocks were transmitted to said second transceiver; and

a receiving buffer configured to receive acknowledgment signals and said identification data from said second transceiver and send said acknowledgment signals and said identification data from said second transceiver to said digital signal processor, wherein a number of data blocks sent by said micro-controller to said digital signal processor is equivalent to a number of said acknowledgment signals received by said receiving buffer.

6. The transceiver according to claim 5 further comprising a timing unit for said data blocks.

7. The transceiver according to claim 5 wherein said transceiver is configured to operate in a General Packet Radio Service (GPRS) network.

8. The transceiver according to claim 5 wherein said transceiver is a mobile station.

9. The transceiver according to claim 5 wherein said micro-controller is configured to provide said data blocks to transmit to said digital signal processor.

10. The transceiver according to claim 7 wherein said micro-controller is configured to provide data blocks of different data packages and said transceiver is configured to transmit said data blocks of different packages via a data frame.

11. The transceiver according to claim 5 wherein said micro-controller is configured to interleavedly communicate with said digital signal processor.

12. The transceiver according to claim 5 wherein said micro-controller employs said index to manage transmission of said data blocks.

13. A transceiver, comprising:

a micro-controller configured to generate at least one data block and identification data associated with said data block, wherein said identification data is an index of a list of said data blocks to be transmitted;

a digital signal processor configured to receive said data block and said identification data from said micro-controller and store said data block until time of transmission to comply with timing requirements of a General Packet Radio Service (GPRS) network, said time of transmission determined by said digital signal processor based on a message received by said transceiver; and

a transmit/receive buffer configured to receive said data block and information data from said digital signal processor for transmission to another transceiver and receive an acknowledgment signal and said information data from said another transceiver, wherein said digital signal processor is configured to send said data block and said information data at said time of transmission to said transmit/receive buffer and send a request to said micro-controller for another data block to be transmitted, said information data including an index of data blocks to be transmitted, said micro-controller further configured to receive said acknowledgment signal and said information data from said transmit/receive buffer and determine a transmission status of said data block based thereon.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED AT REEL: 047195 FRAME: 0827. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Nov 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047924/0571 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0827 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
MERGER Recorded Feb 20, 2015
From: AGERE SYSTEMS INC.
To: AGERE SYSTEMS LLC
Reel/Frame 035058/0895 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035059/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 4, 2003
From: CANNING, NOEL CHARLES; GORIS, NORMAN; MORZINEK, HARALD OLIVER; SCHEIT, WOLFGANG
To: AGERE SYSTEMS INC.
Reel/Frame 014157/0810 →