Split computer architecture
View Patent ↗A network interface is described in which a single computer bus is split over a long distance into two or more inter-communicating buses. On one bus, processing and applications are provided and on the other remote bus, peripheral and local controllers are provided. The buses communicate through a series of: bridge, FPGA, FPGA and bridge. Between the FPGAs, a communication path provides long distance communication.
1. A system comprising a plurality of computer systems, the system comprising:
a plurality of computing systems each located at a first location, wherein each of the computing systems includes:
a CPU;
a memory medium coupled to the CPU;
a first I/O bus coupled to the CPU; and
a first extender coupled to the first I/O bus;
a plurality of human interface systems, wherein each respective one of the human interface systems corresponds to one of the plurality of computing systems, wherein each respective human interface system is located remotely from the first location, wherein each respective human interface system comprises:
a second extender;
a second I/O bus coupled to the second extender;
human interface circuitry coupled to the second I/O bus; and
one or more human interface devices coupled to the human interface circuitry; and
a plurality of transmission mediums, wherein each transmission medium corresponds to a respective computing system and its respective human interface system, wherein each transmission medium couples the first extender of the respective computing system to the respective second extender;
wherein each of the human interface systems is useable by a user to interface with its corresponding computing system;
the system further constructed and adapted to communicate between a said first I/O bus and a said second I/O bus by:
addressing interactive data from the said first I/O bus to a first bridge;
passing the interactive data from the first bridge to a first logic device and in said first logic device:
a) buffering the interactive data in a first FIFO;
b) outputting the interactive data from the first FIFO across a clock domain barrier; and
c) continuing to store the interactive data after said step b);
packeting the interactive data into packet data;
delivering the packet data to a proximate portion of a long distance communication medium;
receiving the packet data at a distal portion of the lone distance communication medium;
depacketing the packet data back into interactive data;
passing the interactive data to a second logic device and in said second logic device:
a) buffering the interactive data in a second FIFO; and
b) outputting the interactive data from the second FIFO received across the clock domain barrier;
receiving the interactive data from the second logic device at a second bridge; and
addressing the interactive data from the second bridge to the second I/O bus.
2. The system of claim 1 , wherein the one or more human interface devices comprise at least one of:
(a) a display monitor, wherein the human interface circuitry includes video display circuitry for providing video signals to the display monitor;
(b) a keyboard, wherein the human interface circuitry includes keyboard circuitry for communicating keyboard signals with the keyboard; and
(c) a pointing device, wherein the human interface circuitry includes pointing device circuitry for communicating pointing device signals with the pointing device.
3. The system of claim 1 , wherein the one or more human interface devices operate as if they were located in the first location and directly connected by human interface cables to the computing system.
4. The system of claim 1 , wherein a transmission medium coupling said first and second extenders comprises a category 5 twisted pairs cable.
5. The system of claim 1 , wherein the first I/O bus and the second I/O bus are the same type of bus.
6. The system of claim 1 , wherein the first I/O bus is a Peripheral Component Interconnect (PCI) bus.
7. The system of claim 1 , wherein the second I/O bus is a Peripheral Component Interconnect (PCI) bus.
8. The system of claim 1 , wherein the first I/O bus is a Peripheral Component Interconnect (PCI) bus, and wherein the second I/O bus is a PCI bus; wherein the first extender, the second extender, and the transmission medium collectively implement a PCI-PCI bridge; and wherein the first extender and the second extender collectively implement a PCI-PCI bridge register set of the PCI-PCI bridge.
9. A method for operating a plurality of computer systems, wherein each of the respective computer systems comprises a computing system and one or more human interface devices, wherein the computing systems of each of the computer systems are commonly located at a first location, wherein the one or more human interface devices for each of the computer systems are located at respective remote locations relative to the first location, wherein, for each of the plurality of computer systems, the method comprising:
receiving user input from a human interface device, wherein the human interface device is located in a second location remote from the first location;
generating first I/O bus signals on a first I/O bus in response to the user input;
generating transmission signals on a transmission medium in response to the first I/O bus signals;
transmitting the transmission signals to a computing system, wherein the computing system is located in the first location, wherein the first location is located remotely from the second location;
the computing system receiving the transmission signals from the transmission medium;
generating second I/O bus signals on a second I/O bus in the computing system in response to the received transmission signals; and
the computing system performing an operation in response to the second I/O bus signals, wherein the operation is in response to the user input, wherein communication between said first I/O bus and said second I/O bus comprises:
addressing interactive data from the said first I/O bus to a fast bridge;
passing the interactive data from the first bridge to a first logic device and in said first logic device:
a) buffering the interactive data in a first FIFO;
b) outputting the interactive data from the fast FIFO across a clock domain barrier; and
c) continuing to store the interactive data after said step b);
packeting the interactive data into packet data;
delivering the packet data to a proximate portion of a long distance communication medium;
receiving the packet data at a distal portion of the long distance communication medium;
depacketing the packet data back into interactive data;
passing the interactive data to a second logic device and in said second logic device:
a) buffering the interactive data in a second FIFO; and
b) outputting the interactive data from the second FIFO received across the clock domain barrier;
receiving the interactive data from the second logic device at a second bridge; and
addressing the interactive data from the second bridge to the second I/O bus.
10. The system of claim 9 , wherein the one or more human interface devices comprise at least one of:
(a) a display monitor, wherein the human interface circuitry includes video display circuitry for providing video signals to the display monitor;
(b) a keyboard, wherein the human interface circuitry includes keyboard circuitry for communicating keyboard signals with the keyboard; and
(c) a pointing device, wherein the human interface circuitry includes pointing device circuitry for communicating pointing device signals with the pointing device.
11. The system of claim 9 , wherein the one or more human interface devices operate as if they were located in the first location and directly connected by human interface cables to the computing system.
12. The system of claim 9 , wherein a transmission medium coupling said first and second extenders comprises a category 5 twisted pairs cable.
13. The system of claim 9 , wherein the first I/O bus and the second I/O bus are the same type of bus.
14. The system of claim 9 , wherein the first I/O bus is a Peripheral Component Interconnect (PCI) bus.
15. The system of claim 9 , wherein the second I/O bus is a Peripheral Component Interconnect (PCI) bus.
16. The system of claim 9 , wherein the first I/O bus is a Peripheral Component Interconnect (PCI) bus, and wherein the second I/O bus is a PCI bus; wherein the first extender, the second extender, and the transmission medium collectively implement a PCI-PCI bridge; and wherein the first extender and the second extender collectively implement a PCI-PCI bridge register set of the PCI-PCI bridge.