Ferroelectric memory and method of operating same
View Patent ↗A ferroelectric memory 636 includes a group of memory cells ( 645, 12, 201, 301, 401, 501 ), each cell having a ferroelectric memory element ( 44, 218, etc.), a drive line ( 122, 322, 422, 522 etc.) on which a voltage for writing information to the group of memory cells is placed, a bit line ( 25, 49, 125, 325, 425, 525, etc.) on which information to be read out of the group of memory cells is placed, a preamplifier ( 20, 42, 120, 320, 420, etc.) between the memory cells and the bit line, a set switch ( 14, 114, 314, 414, 514, etc.) connected between the drive line and the memory cells, and a reset switch ( 16, 116, 316, 416, 516, etc.) connected to the memory cells in parallel with the preamplifier. The memory is read by placing a voltage less than the coercive voltage of the ferroelectric memory element across a memory element. Prior to reading, noise from the group of cells is discharged by grounding both electrodes of the ferroelectric memory element.
1. A ferroelectric memory comprising a memory cell, and a circuit for reading and writing to said memory cell, wherein said circuit for reading and writing includes a drive line on which voltages for writing information to said memory cell and for reading information from said memory cell are placed, a bit line on which information to be read out of said memory cell is placed, a preamplifier having a preamplifier output providing a preamplifier output signal, said preamplifier connected between said memory cell and said bit line with said preamplifier output signal being applied to said bit line, a set switch connected between said drive line and said memory cell, and a reset switch connected to said memory cell.
2. A ferroelectric memory as in claim 1 wherein said preamplifier comprises a transistor having a gate and a pair of source-drains, and wherein said memory cell is connected to said gate, and one of said source-drains is connected to said bit line.
3. A ferroelectric memory as in claim 2 wherein said reset switch is a transistor having a pair of reset source-drains, with one of said reset source-drains connected to said memory cell and the other of said reset source-drains connected to one of said source-drains of said preamplifier transistor.
4. A ferroelectric memory as in claim 1 wherein said set switch is a transistor having a pair of set source-drains, with one of said set source-drains connected to said memory cell and the other of said set source-drains connected to said drive line.
5. A ferroelectric memory as in claim 1 wherein said reset switch is a transistor having a pair of reset source-drains, with one of said reset source-drains connected to said memory cell and the other of said reset source-drains connected to said bit line.
6. A ferroelectric memory as in claim wherein said reset switch is connected in parallel with said preamplifier between said memory cell and said bit line.
7. A ferroelectric memory comprising a plurality of memory cells and a circuit for reading and writing to said memory cells, wherein each of said memory cells comprise a memory cell transistor and a ferroelectric capacitor said memory cell transistor and ferroelectric capacitor connected in parallel, and wherein said circuit for reading and writing includes:
a plurality of read transistors, each of said read transistors including a gate, said gate connected to one of said memory cells;
a source of a reset signal; and
a plurality of reset switches, each of said reset switches connected between said source of a reset signal and said gate of said read transistor.
8. A ferroelectric memory as in claim 7 wherein said reset switches are reset transistors, each of said reset transistors having a pair of reset source-drains, with one of said reset source-drains connected to said source of said reset signal and the other of said reset source-drains connected to said gate of one of said read transistors.
9. A ferroelectric memory comprising a plurality of memory cells and a circuit for reading and writing to said memory cells, wherein each of said memory cells comprise a memory cell transistor and a ferroelectric capacitor said memory cell transistor and ferroelectric capacitor connected in parallel, and wherein said circuit for reading and writing includes:
a source of a set signal; and
a plurality of set switches, each of said set switches connected in series between said one of said memory cells and said source of a set signal.
10. A ferroelectric memory as in claim 9 wherein said set switches are set transistors, each of said set transistors having a pair of set source-drains, with one of said set source-drains connected to said source of said set signal and the other of said set source-drains connected to one of said memory cells.
11. A ferroelectric memory as in claim 1 wherein said memory is a non-destructive read out memory.
12. A ferroelectric memory as in claim 1 wherein said memory is a destructive read out memory.