IP Library Granted Patent US 6,911,361
Granted Patent B2
US 6,911,361 · App. 10/384,846 · Granted Jun 28, 2005

Low temperature processing of PCMO thin film on Ir substrate for RRAM application

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Quick Facts
Patent No.
US 6,911,361
App. No.
10/384,846
Granted
Jun 28, 2005
Kind
B2
Abstract

A method of applying a PCMO thin film on an iridium substrate for use in a RRAM device, includes preparing a substrate; depositing a barrier layer on the substrate; depositing a layer of iridium on the barrier layer; spin coating a layer of PCMO on the iridium; baking the PCMO and substrate in a three-step baking process; post-bake annealing the substrate and the PCMO in a RTP chamber; repeating said spin coating, baking and annealing steps until the PCMO has a desired thickness; annealing the substrate and PCMO; depositing a top electrode; and completing the RRAM device.

Claims (31)

1. A method of applying a PCMO thin film on an iridium substrate for use in a RRAM device, comprising:

preparing a substrate;

depositing a barrier layer on the substrate;

depositing a layer of iridium on the barrier layer;

spin coating a layer of PCMO on the iridium;

baking the PCMO and substrate in a three-step baking process, wherein a temperature for each step in the three-step baking process is higher than the temperature of the previous step;

post-bake annealing the substrate and the PCMO in a RTP chamber;

repeating said spin coating, baking and annealing steps until the PCMO has a desired thickness;

annealing the substrate and PCMO;

depositing a top electrode; and

completing the RRAM device.

2. The method of claim 1 wherein said preparing a substrate includes preparing a silicon substrate having a top layer taken from the group of materials consisting of silicon, silicon dioxide and polysilicon.

3. The method of claim 1 wherein said depositing a barrier layer includes depositing a barrier layer taken from the group of material consisting of Ta, TaN, Ti, TiN, TiAlN, TaAlN, TiSiN, TaSiN, TiAl and TiAlN.

4. The method of claim 1 wherein said spin coating includes selecting a PCMO precursor taken from the group of precursors consisting of Pr(CH 3 CO 2 ) 3 .H 2 O, Ca(CH 3 CO 2 ) 2 .H 2 O, and Mn(III)(CH 3 CO 2 ) 3 .2H 2 O, in an acetic acid solvent.

5. The method of claim 1 wherein said baking the PCMO and substrate in a three-step baking process includes a first baking step at a temperature of between about 50° C. to 150° C. for between about ten seconds and one hour; a second baking step at a temperature of between about 100° C. to 200° C. for between about ten seconds and one hour, and a third baking step at a temperature of between about 150° C. to 300° C. for between about ten seconds and one hour.

6. The method of claim 1 wherein said post-bake annealing the substrate and the PCMO in a RTP chamber includes annealing at a temperature of between about 400° C. to 550° C. for between about ten seconds to one hour.

7. The method of claim 1 wherein said annealing the substrate and PCMO includes annealing the substrate and PCMO at a temperature between about 450° C. to 550° C. for a time of between about one minute to twenty-four hours.

8. A method of applying a PCMO thin film on an iridium substrate for use in a RRAM device, comprising:

preparing a substrate;

depositing a barrier layer on the substrate;

depositing a layer of iridium on the barrier layer;

spin coating a layer of PCMO on the iridium including selecting a PCMO precursor taken from the group of precursors consisting of Pr(CH 3 CO 2 ) 3 .H 2 O, Ca(CH 3 CO 2 ) 2 .H 2 O, and Mn(III)(CH 3 CO 2 ) 3 .2H 2 O, in an acetic acid solvent;

baking the PCMO and substrate in a three-step baking process including a first baking step at a temperature of between about 50° C. to 150° C. for between about ten seconds and one hour; a second baking step at a temperature of between about 100° C. to 200° C. for between about ten seconds and one hour, and a third baking step at a temperature of between about 150° C. to 300° C. for between about ten seconds and one hours, wherein a temperature for each step in the three-step baking process is higher than the temperature of the previous step;

post-bake annealing the substrate and the PCMO in a RTP chamber at a temperature of between about 400° C. to 550° C. for between about ten seconds to one hour;

repeating said spin coating, baking and annealing steps until the PCMO has a desired thickness;

annealing the substrate and PCMO;

depositing a top electrode; and

completing the RRAM device.

9. The method of claim 8 wherein said preparing a substrate includes preparing a silicon substrate having a top layer taken from the group of materials consisting of silicon, silicon dioxide and polysilicon.

10. The method of claim 8 wherein said depositing a barrier layer includes depositing a barrier layer taken from the group of material consisting of Ta, TaN, Ti, TiN, TiAlN, TaAlN, TiSiN, TaSiN, TiAl and TiAlN.

11. The method of claim 8 wherein said annealing the substrate and PCMO includes annealing the substrate and PCMO at a temperature between about 450° C. to 550° C. for a time of between about one minute to twenty-four hours.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2013
From: INTELLECTUAL PROPERTIES I KFT.
To: XENOGENIC DEVELOPMENT LIMITED LIABILITY COMPANY
Reel/Frame 029632/0534 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2013
From: SHARP KABUSHIKI KAISHA
To: INTELLECTUAL PROPERTIES I KFT.
Reel/Frame 029574/0933 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 26, 2012
From: SHARP LABORATORIES OF AMERICA INC.
To: SHARP KABUSHIKI KAISHA
Reel/Frame 028443/0130 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 10, 2003
From: ZHANG, FENGYAN; ZHUANG, WEI-WEI; PAN, WEI; HSU, SHENG TENG
To: SHARP LABORATORIES OF AMERICA, INC.
Reel/Frame 013872/0431 →