IP Library Granted Patent US 6,868,025
Granted Patent B2
US 6,868,025 · App. 10/384,985 · Granted Mar 15, 2005

Temperature compensated RRAM circuit

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Quick Facts
Patent No.
US 6,868,025
App. No.
10/384,985
Granted
Mar 15, 2005
Kind
B2
Abstract

A temperature compensated RRAM sensing circuit to improve the RRAM readability against temperature variations is disclosed. The circuit comprises a temperature dependent element to control the response of a temperature compensated circuit to generate a temperature dependent signal to compensate for the temperature variations of the resistance states of the memory resistors. The temperature dependent element can control the sensing signal supplied to the memory resistor so that the resistance states of the memory resistor are compensated against temperature variations. The temperature dependent element can control the reference signal supplied to the comparison circuit so that the output signal provided by the comparison circuit is compensated against temperature variations. The temperature dependent element is preferably made of the same material and process as the memory resistors.

Claims (51)

1. A temperature compensated RRAM sensing circuit to improve the readability against temperature variations, the circuit comprising:

a) a temperature dependent memory resistor array;

b) a temperature dependent element;

c) a temperature compensated control circuit in communication with the temperature dependent element arid to provide at least one temperature dependent output signal to the temperature dependent memory resistor to compensate for the temperature variation of the resistance of the memory resistor; and

wherein the temperature dependent element is fabricated from the same material and process as the memory resistor.

2. A circuit as in claim 1 , wherein the temperature dependent output signal developed by the temperature compensated control circuit is a temperature dependent current source, the temperature dependency of the current source being in the opposite direction as the temperature dependency of the memory resistor so that the voltage across the memory resistor is compensated against temperature variations.

3. A circuit as in claim 1 , wherein the temperature dependent output signal developed by the temperature compensated control circuit is a temperature dependent voltage source, the temperature dependency of the voltage source being in the same direction as the temperature dependency of the memory resistor so that the current across the memory resistor is compensated against temperature variations.

4. A circuit as in claim 1 , further comprising a sense amplifier, the sense amplifier comprising an inverter.

5. A circuit as in claim 1 , further comprising a sense amplifier, the sense amplifier comprising a comparison circuit.

6. A circuit as in claim 1 , wherein the temperature dependent element is programmed to the lowest resistance state.

7. A circuit as in claim 1 , wherein the temperature compensated control circuit is a current load nMOS circuit.

8. A circuit as in claim 1 , wherein the temperature compensated control circuit is a current load pMOS circuit.

9. A circuit as in claim 1 , wherein the memory resistor array is a 1R1D cross point memory array.

10. A circuit as in claim 1 , wherein the memory resistor array is a 1R1T random access memory array.

11. A circuit as in claim 1 , further comprising a diode connecting to the temperature dependent element.

12. A circuit as in claim 1 , wherein the memory resistor array stores two-bit resistance states.

13. A circuit as in claim 1 , wherein the memory resistor array stores multi-bit resistance states.

14. A circuit as in claim 13 , further comprising a multi-bit sensing circuit.

15. A method to sense a resistance state of a selected memory resistor in an RRAM device to improve the readability against temperature variation, the method comprising the steps of:

a) providing a temperature compensated control circuit comprising a temperature dependent element;

b) developing at least one temperature dependent sensing signal by the temperature compensated control circuit;

c) applying the at least one temperature dependent sensing signal to the memory resistor to compensate for the temperature variation of the resistance of the memory resistor;

d) sensing the compensated state of the memory resistor; and

wherein the temperature dependent element is fabricated from the same material and process as the memory resistor.

16. A method as in claim 15 , wherein the temperature dependent sensing signal is a current source and the compensated state of the memory resistor is the voltage across the memory resistor.

17. A method as in claim 15 , wherein the temperature dependent sensing signal is a voltage source and the compensated state of the memory resistor is the current through the memory resistor.

18. A temperature compensated RRAM sensing circuit to improve the readability against temperature variations, the circuit comprising:

a) a temperature dependent memory resistor array;

b) a temperature dependent element;

c) a temperature compensated control circuit in communication with the temperature dependent element arid to provide at least one temperature dependent output signal to the temperature dependent memory resistor to compensate for the temperature variation of the resistance of the memory resistor; and

wherein the temperature dependent output signal developed by the temperature compensated control circuit is a temperature dependent current source, the temperature dependency of the current source being in the opposite direction as the temperature dependency of the memory resistor so that the voltage across the memory resistor is compensated age net temperature variations.

19. A temperature compensated RRAM sensing circuit to improve the readability against temperature variations, the circuit comprising:

a) a temperature dependent memory resistor array;

b) a temperature dependent element;

c) a temperature compensated control circuit in communication with the temperature dependent element arid to provide at least one temperature dependent output signal to the temperature dependent memory resistor to compensate for the temperature variation of the resistance of the memory resistor; and

wherein the temperature dependent output signal developed by the temperature compensated control circuit is a temperature dependent voltage source, the temperature dependency of the voltage source being in the same direction as the temperature dependency of the memory resistor so that the current across the memory resistor is compensated against temperature variations.

20. A temperature compensated RRAM sensing circuit to improve the readability against temperature variations, the circuit comprising:

a) a temperature dependent memory resistor array;

b) a temperature dependent element;

c) a temperature compensated control circuit in communication with the temperature dependent element arid to provide at least one temperature dependent output signal to the temperature dependent memory resistor to compensate for the temperature variation of the resistance of the memory resistor; and

wherein the temperature compensated control circuit is a current load nMOS circuit.

21. A temperature compensated RRAM sensing circuit to improve the readability against temperature variations, the circuit comprising:

a) a temperature dependent memory resistor array;

b) a temperature dependent element;

c) a temperature compensated control circuit in communication with the temperature dependent element arid to provide at least one temperature dependent output signal to the temperature dependent memory resistor to compensate for the temperature variation of the resistance of the memory resistor; and

wherein the temperature compensated control circuit is a current source pMOS circuit.

22. A temperature compensated RRAM sensing circuit to improve the readability against temperature variations, the circuit comprising:

a) a temperature dependent memory resistor array;

b) a temperature dependent element;

c) a temperature compensated control circuit in communication with the temperature dependent element arid to provide at least one temperature dependent output signal to the temperature dependent memory resistor to compensate for the temperature variation of the resistance of the memory resistor; and

d) a diode connecting to the temperature dependent element.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2013
From: INTELLECTUAL PROPERTIES I KFT.
To: XENOGENIC DEVELOPMENT LIMITED LIABILITY COMPANY
Reel/Frame 029632/0534 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2013
From: SHARP KABUSHIKI KAISHA
To: INTELLECTUAL PROPERTIES I KFT.
Reel/Frame 029574/0933 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 26, 2012
From: SHARP LABORATORIES OF AMERICA INC.
To: SHARP KABUSHIKI KAISHA
Reel/Frame 028442/0996 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 10, 2003
From: HSU, SHENG TENG
To: SHARP LABORATORIES OF AMERICA, INC.
Reel/Frame 013870/0173 →