IP Library Granted Patent US 7,336,717
Granted Patent B2
US 7,336,717 · App. 10/384,996 · Granted Feb 26, 2008

Receiver circuit, in particular for a mobile radio

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Quick Facts
Patent No.
US 7,336,717
App. No.
10/384,996
Granted
Feb 26, 2008
Kind
B2
Abstract

A radio receiver with a low intermediate frequency has a first mixer stage that can be fed with a modulated input signal and at whose output a complex intermediate frequency signal can be derived. Connected downstream of the first mixer stage is a limiting amplifier at whose output the intermediate frequency signal is present in a discrete-value and continuous-time fashion. A sampling device, for sampling the intermediate frequency signal, and a digital demodulator unit are connected to the output of this limiter. The demodulated input signal can be derived at the output of this digital demodulator unit. The present radio receiver requires a low chip area in conjunction with low power consumption, but offers a high sensitivity and accuracy based on the digitally implemented demodulation.

Claims (26)

1. A receiver circuit for demodulating a radio-frequency signal, comprising:

a first mixer stage having a first input, a second input, and an output, said first input for obtaining a radio-frequency signal to be demodulated, said second input for obtaining a complex-value carrier signal, said output for providing a complex-valued intermediate frequency signal;

a limiting amplifier connected to said output of said first mixer stage, said limiting amplifier having an output for providing a discrete-value signal derived from the intermediate frequency signal;

a sampling device connected to said output of said limiting amplifier;

a channel filter designed as a polyphase filter configured between said first mixer stage and said limiting amplifier; and

a digital demodulator unit connected downstream of said sampling device, said demodulator unit having an output for providing a demodulated signal.

2. The receiver circuit according to claim 1 , wherein the intermediate frequency signal has a frequency of less than or equal to 20 MHz.

3. The receiver circuit according to claim 2 , wherein said digital demodulator unit has a bandpass filter and a digital demodulator connected downstream from said bandpass filter.

4. The receiver circuit according to claim 1 , wherein said digital demodulator unit has a bandpass filter and a digital demodulator connected downstream from said bandpass filter.

5. The receiver circuit according to claim 4 , wherein said bandpass filter is a polyphase filter.

6. The receiver circuit according to claim 5 , wherein said digital demodulator is a quadricorrelator.

7. The receiver circuit according to claim 4 , wherein said digital demodulator is a quadricorrelator.

8. The receiver circuit according to claim 1 , wherein:

said digital demodulator unit has a digital mixer stage, a lowpass filter, and digital demodulator; and

said lowpass filter and said digital demodulator are connected downstream from said digital mixer stage.

9. The receiver circuit according to claim 1 , wherein:

said digital demodulator unit has a digital mixer stage, a lowpass filter, and digital demodulator;

said lowpass filter and said digital demodulator are connected downstream from said digital mixer stage; and

the intermediate frequency signal has a frequency of less than or equal to 20 MHz.

10. The receiver circuit according to claim 1 , further comprising a low-noise preamplifier for connecting said first input of said first mixer stage to an antenna.

11. A receiver circuit for being implemented in a mobile radio and for demodulating a radio-frequency signal, comprising:

a first mixer stage having a first input, a second input, and an output, said first input for obtaining a radio-frequency signal to be demodulated, said second input for obtaining a complex-value carrier signal, said output for providing a complex-valued intermediate frequency signal;

a limiting amplifier connected to said output of said first mixer stage, said limiting amplifier having an output for providing a discrete-value signal derived from the intermediate frequency signal;

a sampling device connected to said output of said limiting amplifier;

a channel filter designed as a polyphase filter configured between said first mixer stage and said limiting amplifier; and

a digital demodulator unit connected downstream of said sampling device, said demodulator unit having an output for providing a demodulated signal.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2020
From: INTEL CORPORATION
To: APPLE INC.
Reel/Frame 053518/0586 →
CONFIRMATORY ASSIGNMENT EFFECTIVE AS OF JANUARY 1, 2018 Recorded Aug 12, 2020
From: INTEL DEUTSCHLAND GMBH
To: INTEL CORPORATION
Reel/Frame 053477/0001 →
CHANGE OF NAME Recorded Nov 6, 2015
From: INTEL MOBILE COMMUNICATIONS GMBH
To: INTEL DEUTSCHLAND GMBH
Reel/Frame 037057/0061 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2012
From: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
To: INTEL MOBILE COMMUNICATIONS GMBH
Reel/Frame 027556/0709 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2012
From: INFINEON TECHNOLOGIES AG
To: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
Reel/Frame 027548/0623 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE ADDRESS INFINEON TECHNOLOGIES AG, ST.-MARTIN-STRASSE 53,D-81669 MUENCHEN, GERMAN DEMOCRATIC REPUBLIC. PREVIOUSLY RECORDED ON REEL 020179 FRAME 0100. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECT ASSIGNEE ADDRESS IS INFINEON TECHNOLOGIES AG, ST.-MARTIN-STRASSE 53 D-81669 MUENCHEN, GERMANY.. Recorded Apr 1, 2011
From: HAMMES, MARKUS; HEINEN, STEFAN; WAASEN, STEFAN VAN; HANKE, ANDRE; MEHRGARDT, SOENKE; WAGNER, ELMAR
To: INFINEON TECHNOLOGIES AG
Reel/Frame 026067/0227 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 30, 2007
From: HAMMES, MARKUS; HEINEN, STEFAN; WAASEN, STEFAN VAN; HANKE, ANDRE; MEHRGARDT, SOENKE; WAGNER, ELMAR
To: INFINEON TECHNOLOGIES AG
Reel/Frame 020179/0100 →