Receiver circuit, particularly for mobile radio
View Patent ↗In a receiver circuit for demodulating a high-frequency signal, a limiting amplifier stage with a downstream sigma-delta converter is connected in series with a mixer stage that transforms a high-frequency signal that is supplied at its input into an intermediate-frequency signal. The intermediate-frequency signal at the output of the limiting amplifier stage is value-discrete and time-continuous. The described receiver architecture has a high sensitivity, is substantially independent of production tolerances, and occupies a small area; therefore, it is particularly suitable for mobile radio applications.
1. A receiver circuit, comprising: a mixer stage having an input for receiving a high-frequency signal to be demodulated, and an output outputting a complex-value intermediate frequency signal derived from the high-frequency signal;
a limiting amplifier stage disposed downstream of said mixer stage, said limiting amplifier stage receiving the complex-value intermediate-frequency signal and having an output outputting a value-discrete, complex-value signal derived from the complex-value intermediate-frequency signal;
a sigma-delta converter directly connected to said output of said limiting amplifier stage for converting the value-discrete, complex-value signal outputted by said limiting amplifier stage into a value-discrete and time discrete signal; and
a polyphase filter for channel selection disposed between said mixer stage and said limiting amplifier stage.
2. The receiver circuit according to claim 1 , further comprising a digital demodulator, and said sigma-delta converter having an output coupled to said digital demodulator.
3. The receiver circuit according to claim 1 , further comprising a decimation element disposed downstream of said sigma-delta converter.
4. The receiver circuit according to claim 1 , wherein said sigma-delta converter is a time-continuous bandpass sigma-delta modulator.
5. The receiver circuit according to claim 1 , wherein said sigma-delta converter has a further polyphase filter for filtering a complex frequency spectrum.
6. The receiver circuit according to claim 1 , wherein a frequency level of the complex-value intermediate-frequency signal is less than or equal to 20 MHz.
7. The receiver circuit according to claim 1 , further comprising an antenna connected to said input of said mixer stage.
8. The receiver circuit according to claim 1 , wherein said mixer stage has a further input for receiving a complex carrier signal.