Method and system for deterministic control of an emulation
View Patent ↗An emulation-based event-wait simulator including an application module to configure and command verification processes on a design under test (DUT). An event dispatcher is in communication with the application module to deliver commands to the DUT. A plurality of transactors are in communication with the event dispatcher to forward the commands to the DUT. A channel controller is in communication with the transactors to process and forward the commands to the DUT, wherein the channel controller also receives messages from the DUT, processes the messages, and forwards the messages to the transactors for delivery to the event dispatcher and the application module.
1. A system for evaluating performance of a device under test (DUT) comprising:
an application module that generates transactions used to test the DUT;
a plurality of hardware transactors coupled to the application module that transmit and receive data representing the transactions to and from the DUT; and
an emulator coupled to the hardware transactors, the emulator including the DUT and having an emulation clock that is controlled by the application module,
wherein the application module waits for events from the emulator in zero simulation time, receives timing information from the emulator concerning status of the emulation clock, and controls operation of the emulation clock by restarting the emulation clock, and
wherein the hardware transactors stop the clock, gather the data while the clock is stopped, and forward the data to multiple output channels simultaneously when the clock is restarted, wherein multiple, independent parallel transactions are executed;
wherein the starting and stopping of the clock is accurate to within one clock cycle; and
wherein the events can be viewed in real-time or recorded for later review and comparison with a set of predicted events to evaluate performance of the DUT.
2. The system of claim 1 , wherein the application module provides information to the emulator indicating how many cycles the emulation clock should run for.
3. The system of claim 1 , wherein the emulation clock runs in a deterministic manner.
4. The system of claim 1 , wherein the operations of the DUT can be halted to an accuracy of one processing cycle.
5. The system of claim 1 , wherein the emulator includes a channel controller that communicates a status of the emulation clock to the application module.
6. The system of claim 5 , wherein the emulation clock is advanced by a number of cycles received in a command from the application module.
7. The system of claim 1 , wherein the emulator includes a channel controller that sends priority encoded messages to the application module.
8. The system of claim 1 , wherein the emulation clock is advanced by a number of cycles received in a command from the application module.
9. A method for deterministically evaluating operations of a circuit design comprising:
selecting transactions for communication over multiple channels with an emulator of the circuit design;
awaiting event notifications from the emulator regarding service requests;
receiving responses from the emulator based on the transactions;
controlling a clock that can be started by an application module and that can be stopped by a hardware transactor, wherein the starting and stopping of the clock is accurate to within one clock cycle; and
upon receiving a response that requires service by the application module, stopping the clock and entering an event-wait state corresponding to zero simulation time while servicing the response that requires service, gathering data while the clock is stopped, and forwarding the data to multiple output channels simultaneously when the clock is restarted, wherein multiple, independent parallel transactions are executed;
wherein the responses can be viewed in real-time or recorded for later review and comparison with a set of expected or predicted responses to evaluate performance of the circuit design.
10. A system for evaluating performance of a device under test (DUT) comprising:
means for generating transactions used to test a DUT having one or more input and one or more output channels;
means for receiving data packets sent from an application module to a deterministic emulator that includes a channel controller;
means for controlling a clock, which can be started by an application module and which can be stopped by one of a plurality of hardware transactors, within the deterministic emulator to allow for synchronous operation without latency effects, the clock being responsive to commands from the application module, wherein the starting and stopping of the clock is accurate to within one clock cycle; and
means for forwarding the data packets from the application module through the plurality of transactors to multiple output channels to be transferred to the DUT, wherein the transactors gather the data packets while the clock is stopped, and forward the data packets to the multiple output channels simultaneously when the clock is restarted wherein multiple, independent parallel transactions are executed;
wherein events contained in the data packets can be viewed in real-time or recorded for later review and comparison with a set of expected or predicted events to evaluate performance of the DUT.