General-purpose logic array and ASIC using the same
View Patent ↗A general-purpose logic cell array includes a plurality of cells and a lower wiring layer. The plurality of cells are formed on a substrate, and each of the plurality of cells includes a plurality of transistors. The lower wiring layer is formed above the plurality of cells, and which connects the plurality of transistors in each of the plurality of cells such that each of the plurality of cells has an elementary logic circuit. Information of the general-purpose logic cell array is provided to a user. The elementary logic circuits may be one of a gate circuit, a selector, an inverter and a flip-flop.
1. A general purpose logic cell array comprising:
a plurality of cells which are formed on a substrate, each of said plurality of cells including a plurality of transistors; and
at least one first wiring layer which connects said plurality of transistors in each of said plurality of cells such that each of said plurality of cells has an elementary logic circuit,
wherein said plurality of cells comprises a plurality of different types of elementary logic circuits, cells having the same elementary logic circuit are grouped together,
wherein said plurality of cells are grouped into a plurality of groups based on an elementary logic function corresponding to said elementary logic circuit, and
said cells of each of said plurality of groups are arranged in a first direction to form a row,
wherein rows of said cells of said plurality of groups are cyclically arranged in a second direction orthogonal to said first direction.
2. A general purpose logic cell array comprising:
a plurality of cells which are formed on a substrate, each of said plurality of cells including a plurality of transistors; and
at least one first wiring layer which connects said plurality of transistors in each of said plurality of cells such that each of said plurality of cells has an elementary logic circuit,
wherein said plurality of cells comprises a plurality of different types of elementary logic circuits, cells having the same elementary logic circuit are grouped together,
wherein at least one transistor connected to an input terminal of said elementary logic circuit has a smaller size and a smaller input capacitor than at least one transistor connected to an output terminal of said elementary circuit.
3. A general purpose logic cell array comprising:
a plurality of cells which are formed on a substrate, each of said plurality of cells including a plurality of transistors; and
at least one first wiring layer which connects said plurality of transistors in each of said plurality of cells such that each of said plurality of cells has an elementary logic circuit,
wherein said plurality of cells comprises a plurality of different types of elementary logic circuits, cells having the same elementary logic circuit are grouped together,
wherein at least one transistor connected to an output terminal of said elementary logic circuit has a larger size and a larger drive capability than at least one transistor connected to an input terminal of said elementary circuit.
4. A general purpose logic cell array comprising:
a plurality of cells which are formed on a substrate, each of said plurality of cells including a plurality of transistors; and
at least one first wiring layer which connects said plurality of transistors in each of said plurality of cells such that each of said plurality of cells has an elementary logic circuit,
wherein said plurality of cells comprises a plurality of different types of elementary logic circuits, cells having the same elementary logic circuit are grouped together,
wherein the grouped cells are arranged in at least one linear array.
5. The general purpose logic cell array as in any one of claims 1 , 2 , 3 and 4 , wherein said elementary logic circuits is one of a gate circuit, a selector, an inverter and a flip-flop.
6. An ASIC comprising:
a plurality of cells which are formed on a substrate, each of said plurality of cells including a plurality of transistors;
at least one first wiring layer which connects said plurality of transistors in each of said plurality of cells such that each of said plurality of cells has an elementary logic circuit; and
at least one second wiring layer connecting said elementary logic circuits based on a logic function desired by a user,
wherein said plurality of cells comprises a plurality of different types of elementary logic circuits, cells having the same elementary logic circuit are grouped together,
wherein said plurality of cells are grouped into a plurality of groups based on an elementary logic function corresponding to said elementary logic circuit, and
said cells of each of said plurality of groups are arranged in a first direction to form a row,
wherein rows of said cells of said plurality of groups are cyclically arranged in a second direction orthogonal to said first direction.
7. An ASIC comprising:
a plurality of cells which are formed on a substrate, each of said plurality of cells including a plurality of transistors;
at least one first wiring layer which connects said plurality of transistors in each of said plurality of cells such that each of said plurality of cells has an elementary logic circuit; and
at least one second wiring layer connecting said elementary logic circuits based on a logic function desired by a user,
wherein said plurality of cells comprises a plurality of different types of elementary logic circuits, cells having the same elementary logic circuit are grouped together,
wherein at least one transistor connected to an input terminal of said elementary logic circuit has a smaller size and a smaller input capacitor than at least one transistor connected to an output terminal of said elementary circuit.
8. An ASIC comprising:
a plurality of cells which are formed on a substrate, each of said plurality of cells including a plurality of transistors;
at least one first wiring layer which connects said plurality of transistors in each of said plurality of cells such that each of said plurality of cells has an elementary logic circuit; and
at least one second wiring layer connecting said elementary logic circuits based on a logic function desired by a user,
wherein said plurality of cells comprises a plurality of different types of elementary logic circuits, cells having the same elementary logic circuit are grouped together,
wherein at least one transistor connected to an output terminal of said elementary logic circuit has a larger size and a larger drive capability than at least one transistor connected to an input terminal of said elementary circuit.
9. An ASIC comprising:
a plurality of cells which are formed on a substrate, each of said plurality of cells including a plurality of transistors;
at least one first wiring layer which connects said plurality of transistors in each of said plurality of cells such that each of said plurality of cells has an elementary logic circuit; and
at least one second wiring layer connecting said elementary logic circuits based on a logic function desired by a user,
wherein said plurality of cells comprises a plurality of different types of elementary logic circuits, cells having the same elementary logic circuit are grouped together,
wherein the grouped cells are arranged in at least one linear array.
10. The ASIC as in any one of claims 6 , 7 , 8 and 9 , wherein said elementary logic circuits is one of a gate circuit, a selector, an inverter and a flip-flop.
11. A method of manufacturing a general purpose logic cell array, comprising the steps of:
(a) forming on a substrate, a plurality of cells, each of which includes a plurality of transistors; and
(b) forming a at least one first wiring layer to connect said plurality of transistors in each of said plurality of cells and to produce an elementary logic circuit in each of said plurality of cells,
wherein said plurality of cells comprises a plurality of different types of elementary logic circuits, cells having the same elementary logic circuit are grouped together,
wherein said plurality of cells are grouped into a plurality of groups based on an elementary logic function corresponding to said elementary logic circuit, and
said (a) forming step comprises the step of:
arranging said cells of each of said plurality of groups in a first direction to form a row,
wherein said (a) forming step comprises the step of:
cyclically arranging rows of said cells of said plurality of groups in a second direction orthogonal to said first direction.
12. A method of manufacturing a general purpose logic cell array, comprising the steps of:
(a) forming on a substrate, a plurality of cells, each of which includes a plurality of transistors; and
(b) forming a at least one first wiring layer to connect said plurality of transistors in each of said plurality of cells and to produce an elementary logic circuit in each of said plurality of cells,
wherein said plurality of cells comprises a plurality of different types of elementary logic circuits, cells having the same elementary logic circuit are grouped together,
wherein said (a) forming step comprises the step of:
forming each of said transistors in each of said plurality of cells such that at least one transistor connected to an input terminal of said elementary logic circuit has a smaller size and a smaller input capacitor than at least one transistor connected to an output terminal of said elementary circuit.
13. A method of manufacturing a general purpose logic cell array, comprising the steps of:
(a) forming on a substrate, a plurality of cells, each of which includes a plurality of transistors; and
(b) forming a at least one first wiring layer to connect said plurality of transistors in each of said plurality of cells and to produce an elementary logic circuit in each of said plurality of cells,
wherein said plurality of cells comprises a plurality of different types of elementary logic circuits, cells having the same elementary logic circuit are grouped together,
wherein said (a) forming step comprises the step of:
forming each of said transistors in each of said plurality of cells such that at least one transistor connected to an output terminal of said elementary logic circuit has a larger size and a larger drive capability than at least one transistor connected to an input terminal of said elementary circuit.
14. A method of manufacturing a general purpose logic cell array, comprising the steps of:
(a) forming on a substrate, a plurality of cells, each of which includes a plurality of transistors; and
(b) forming a at least one first wiring layer to connect said plurality of transistors in each of said plurality of cells and to produce an elementary logic circuit in each of said plurality of cells,
wherein said plurality of cells comprises a plurality of different types of elementary logic circuits, cells having the same elementary logic circuit are grouped together,
wherein the grouped cells are arranged in at least one linear array.
15. The method according to any one of claims 11 , 12 , 13 and 14 , wherein said elementary logic circuits is one of a gate circuit, a selector, an inverter and a flip-flop.
16. A method of manufacturing an ASIC, comprising the steps of:
(a) forming a general purpose logic cell array comprising a plurality of cells on a substrate;
(b) forming at least one first wiring layer to provide a plurality of different types of elementary logic circuits, cells having the same elementary logic circuit are grouped together;
(c) designing a layout of at least one second wiring layer based on a logic function desired by a user; and
(d) forming said at least one second wiring layer to connect said elementary logic circuits based on said layout of said at least one second wiring layer,
wherein said (a) forming step comprises:
(e) forming said plurality of cells such that each of said plurality of cells includes a plurality of transistors; and
wherein said at least one first wiring layer formed in step (b) connects said plurality of transistors in each of said plurality of cells to produce an elementary logic circuit in each of said plurality of cells,
wherein said plurality of cells are grouped into a plurality of groups based on an elementary logic function corresponding to said elementary logic circuit, and
said (e) forming step comprises the step of:
arranging said cells of each of said plurality of groups in a first direction to form a row,
wherein said (e) forming step comprises the step of:
cyclically arranging rows of said cells of said plurality of groups in a second direction orthogonal to said first direction.
17. A method of manufacturing an ASIC, comprising the steps of:
(a) forming a general purpose logic cell array comprising a plurality of cells on a substrate;
(b) forming at least one first wiring layer to provide a plurality of different types of elementary logic circuits, cells having the same elementary logic circuit are grouped together;
(c) designing a layout of at least one second wiring layer based on a logic function desired by a user; and
(d) forming said at least one second wiring layer to connect said elementary logic circuits based on said layout of said at least one second wiring layer,
wherein said (a) forming step comprises:
(e) forming said plurality of cells such that each of said plurality of cells includes a plurality of transistors; and
wherein said at least one first wiring layer formed in step (b) connects said plurality of transistors in each of said plurality of cells to produce an elementary logic circuit in each of said plurality of cells,
wherein said (e) forming step comprises the step of:
forming each of said transistors in each of said plurality of cells such that at least one transistor connected to an input terminal of said elementary logic circuit has a smaller size and a smaller input capacitor than at least one transistor connected to an output terminal of said elementary circuit.
18. A method of manufacturing an ASIC, comprising the steps of:
(a) forming a general purpose logic cell array comprising a plurality of cells on a substrate;
(b) forming at least one first wiring layer to provide a plurality of different types of elementary logic circuits, cells having the same elementary logic circuit are grouped together;
(c) designing a layout of at least one second wiring layer based on a logic function desired by a user; and
(d) forming said at least one second wiring layer to connect said elementary logic circuits based on said layout of said at least one second wiring layer,
wherein said (a) forming step comprises:
(e) forming said plurality of cells such that each of said plurality of cells includes a plurality of transistors; and
wherein said at least one first wiring layer formed in step (b) connects said plurality of transistors in each of said plurality of cells to produce an elementary logic circuit in each of said plurality of cells,
wherein said (e) forming step comprises the step of:
forming each of said transistors in each of said plurality of cells such that at least one transistor connected to an output terminal of said elementary logic circuit has a larger size and a larger drive capability than at least one transistor connected to an input terminal of said elementary circuit.
19. A method of manufacturing an ASIC, comprising the steps of:
(a) forming a general purpose logic cell array comprising a plurality of cells on a substrate;
(b) forming at least one first wiring layer to provide a plurality of different types of elementary logic circuits, cells having the same elementary logic circuit are grouped together;
(c) designing a layout of at least one second wiring layer based on a logic function desired by a user; and
(d) forming said at least one second wiring layer to connect said elementary logic circuits based on said layout of said at least one second wiring layer,
wherein the grouped cells are arranged in at least one linear array.
20. The method as in any one of claims 16 , 17 , 18 and 19 , wherein said elementary logic circuits is one of a gate circuit, a selector, an inverter and a flip-flop.