Differental current source for generating DRAM refresh signal
View Patent ↗A circuit for generating a refresh signal for a memory cell of a semiconductor memory includes a capacitor and a differential current source for providing a charging current to the capacitor. The differential current source includes a temperature-dependent and a temperature-independent current source connected such that the charging current is proportional to a difference between a temperature-dependent current and a temperature-independent current. A comparator a voltage at a capacitor terminal and a reference voltage. The comparator generates a refresh signal when capacitor voltage exceeds the reference voltage.
1. A circuit for generating a refresh signal for a memory cell of a semiconductor memory, the circuit comprising:
a capacitor;
a differential current source for providing a charging current to the capacitor, the differential current source including:
a temperature-dependent current source for providing a temperature-dependent current, and
a temperature-independent current source for providing a temperature-independent current,
the temperature-dependent current source and the temperature-independent current source being connected such that the charging current is proportional to a difference between the temperature-dependent current and the temperature-independent current; and
a comparator having
a capacitor input connected to a first terminal of the capacitor, and
a reference input connected to a reference voltage,
the comparator being configured to generate a refresh signal when the voltage present at the capacitor input exceeds the voltage present at the reference input.
2. The circuit of claim 1 , further comprising a switch for resetting the capacitor.
3. The circuit of claim 2 , wherein the switch is configured to reset the capacitor when the comparator generates the refresh signal.
4. The circuit of claim 1 , wherein the temperature-dependent current source is configured to generate a temperature-dependent current that is proportional to a current of a bandgap circuit associated with the semiconductor memory.
5. The circuit of claim 1 , wherein the temperature-dependent current source comprises a first current mirror configured to mirror a temperature-dependent current.
6. The circuit of claim 5 , wherein the first current mirror is configured to multiply a temperature-dependent current.
7. The circuit of claim 5 , further comprising a second current mirror configured to mirror an output current of the first current mirror.
8. The circuit of claim 1 , wherein the temperature-independent current source comprises a current mirror configured to mirror a temperature-independent current.
9. The circuit of claim 1 , wherein the memory cell comprises a DRAM memory cell.
10. A DRAM memory having a memory cell configured to receive a refresh signal from the circuit of claim 1 .
11. The circuit of claim 1 , further comprising a temperature-independent voltage source configured to maintain a temperature-independent voltage at a second terminal of the capacitor, and wherein the first terminal of the capacitor is connected to the differential current source.
12. A method for generating a refresh signal for a memory cell of a semiconductor memory, the method comprising:
charging a capacitor with a current proportional to a difference between a temperature-dependent current and a temperature-independent current;
comparing a voltage at the capacitor with a reference voltage; and outputting the refresh signal when a capacitor voltage exceeds the reference voltage.
13. The method of claim 12 , further comprising resetting the capacitor concurrently with outputting the refresh signal.
14. A circuit for providing a refresh signal to a memory cell, the circuit comprising:
a temperature-dependent oscillator configured to periodically generate a refresh signal at a frequency that depends on a temperature of the memory cell, the temperature-dependent oscillator including
a capacitor;
a switch connected across the capacitor for periodically discharging the capacitor; and
a comparator having:
a capacitor input connected to a first terminal of the capacitor, and
a reference input connected to a reference voltage,
a refresh signal output in communication with the memory cell, and
a reset signal output in communication with the switch,
the comparator being configured to, when the voltage present at the capacitor input exceeds the voltage present at the reference input,
generate a refresh signal to be provided to the memory cell, and
generate a reset signal to cause the switch to discharge the capacitor; and
means for providing, to the oscillator, a signal indicative of the temperature of the memory cell.