Video bus for a video decoding system
View Patent ↗Systems and methods are disclosed for a bus, link or interface. More specifically, systems and methods are discloses for a bus, link or interface adapted to transmit data and control information to at least one processing module and provide synchronization between the data and the control information without requiring the transmission of blank pixels or timing information.
1. A bus adapted to transmit pixel data and control information to at least one processing module and provide synchronization between the pixel data and the control information without requiring the transmission of blank pixels or timing information, wherein the bus is adapted to transmit pixel data processed by the processing module from the processing module at a rate independent of a processing rate of the pixel data by the processing module to another processing module;
wherein the bus is adapted to transmit the pixel data in accordance with a protocol to prevent pixel data overrun in the processing module, wherein said protocol comprises transmitting accept and reject signals;
wherein the data is transmitted to the another processing module at a rate faster than processed by the another processing module; and
wherein the bus is adapted to transmit pixel data and at least one additional packet of data every field time.
2. The bus of claim 1 , wherein the processing module uses the pixel data and control information to process a field of data.
3. The bus of claim 1 , wherein said at least one additional packet of data comprises indicators indicating the beginning data byte for each line.
4. The bus of claim 1 , wherein said pixel data is stored in a storage element in the processing module prior to processing.
5. The bus of claim 1 adapted to provide pixel data to at least two video processing modules.
6. The bus of claim 1 adapted to enable simultaneous transmission of multiple lines of video.
7. The bus of claim 6 , wherein additional data is communicated with each said line of video.
8. The bus of claim 1 adapted to support more than one implementation width.
9. The bus of claim 8 further adapted to support implementation widths of 8, 16 and 32 bits of pixel data.
10. The bus of claim 1 adapted to provide multiple types of pixel data to the processing module.
11. The bus of claim 1 , wherein the bus is adapted to transmit data from the processing module to the another processing module during assertion of the an accept signal from the another processing module, wherein the bus is adapted to stop transmitting data from the processing module to the another processing module during deassertion of the accept signal from the another processing module, wherein the accept signal is deasserted upon detection of a condition indicating that a data overrun is likely to occur.
12. The bus of claim 1 , wherein the pixel data is transmitted as a contiguous array of pixel data comprising a two or more lines of pixel data.
13. The bus of claim 1 , wherein said at least one additional packet of data comprises user data.