Frequency synthesizer with prescaler

1. A frequency synthesizer comprising:

a voltage controlled oscillator for generating an output signal having a synthesized frequency; and

a prescaler connected to the VCO for receiving the output signal and providing a feedback signal; wherein:

the prescaler programmatically selects between an integer divider value and a fractional divider value to divide the synthesized frequency of the output signal; and

the integer divider value is a first integer divider value; and the prescaler corrects an error introduced by the fractional divider by programmatically selecting between a second integer divider value and a third integer divider value.

2. A frequency synthesizer comprising:

a voltage controlled oscillator for generating an output signal having a synthesized frequency; and

a prescaler connected to the VCO for receiving the output signal and providing a feedback signal; wherein:

the prescaler programmatically selects between an integer divider value and a fractional divider value to divide the synthesized frequency of the output signal; and

the prescaler includes a first counter having a first counter output and a second counter having a second counter output.

3. A frequency synthesizer as recited in claim 2 wherein the prescaler corrects an error introduced by the fractional divider.

4. A frequency synthesizer as recited in claim 1 wherein the prescaler corrects an error introduced by the fractional divider by adjusting an output clock period.

5. A frequency synthesizer as recited in claim 2 wherein the prescaler corrects an error introduced by the fractional divider by extending an output clock period.

6. A frequency synthesizer as recited in claim 2 wherein the prescaler divides the synthesized frequency to produce a clock signal.

7. A frequency synthesizer as recited in claim 2 wherein the prescaler divides the synthesized frequency to produce a clock signal; and the prescaler corrects an error introduced by the fractional divider value by extending a period of the clock signal.

8. A frequency synthesizer as recited in claim 2 wherein the frequency synthesizer is included in a wireless transceiver device supporting IEEE 802.11a protocol.

9. A frequency synthesizer as recited in claim 2 wherein the frequency synthesizer is included in a wireless transceiver device supporting IEEE 802.11b protocol.

10. A frequency synthesizer comprising:

a voltage controlled oscillator for generating an output signal having a synthesized frequency; and

a prescaler connected to the VCO for receiving the output signal and providing a feedback signal; wherein:

the prescaler programmatically selects between an integer divider value and a fractional divider value to divide the synthesized frequency of the output signal; and

the prescaler includes a first counter having a first counter output and a second counter having a second counter output; and the prescaler programmatically selects between the integer divider value and the fractional divider value based on the first counter output and the second counter output.

11. A frequency synthesizer comprising:

a voltage controlled oscillator for generating an output signal having a synthesized frequency; and

a prescaler connected to the VCO for receiving the output signal and providing a feedback signal; wherein:

the prescaler programmatically selects between an integer divider value and a fractional divider value to divide the synthesized frequency of the output signal; and

the prescaler includes a first counter having a first counter output and a second counter having a second counter output; and the prescaler corrects an error introduced by the fractional divider using the first counter output and the second counter output.

12. A frequency synthesizer comprising:

a voltage controlled oscillator for generating an output signal having a synthesized frequency; and

a prescaler connected to the VCO for receiving the output signal and providing a feedback signal; wherein:

the prescaler programmatically selects between an integer divider value and a fractional divider value to divide the synthesized frequency of the output signal;

the output frequency corresponds to a frequency channel within a frequency band;

the frequency band is determined by number of times the integer divider value is selected; and

the frequency channel is determined by number of times the fractional divider value is selected.

13. A prescaler comprising:

an input interface for receiving an input signal with a frequency;

a first divider configured to divide the input signal;

a first counter having a first counter output; and

a second counter having a second counter output;

wherein:

the first divider programmatically selects between an integer divider value and a fractional divider value to divide the input signal.

14. A prescaler as recited in claim 13 wherein the prescaler is used for generating a feedback signal in a frequency synthesizer.

15. A prescaler comprising:

an input interface for receiving an input signal with a frequency;

a first divider configured to divide the input signal; and

a second divider; wherein:

the first divider programmatically selects between an integer divider value and a fractional divider value to divide the input signal;

the first divider outputs a clock signal; and

the second divider is configured to correct the clock signal.

16. A method for synthesizing an output signal having a synthesized frequency including:

receiving a voltage controlled oscillator output having a frequency;

dividing the frequency of the voltage controlled oscillator output by programmatically selecting between an integer divider value and a fractional divider value; and

producing a feedback signal for controlling frequency of the output signal; wherein

programmatically selecting is based on a first counter output and a second counter output.