Liquid crystal displays using organic insulating material for a gate insulating layer and/or having photolithographic formed spacers
View Patent ↗A passivation layer is formed by coating a flowable insulating material on the substrate where a thin film transistor and a storage capacitor electrode, and a pixel electrode is formed on the passivation layer. A portion of the passivation layer is etched using the pixel electrode as a mask to make a groove on the thin film transistor, and then a black matrix is formed by filling an organic black photoresist in the groove. To increase the storage capacitance, a portion of the passivation layer is removed or to form a metal pattern on the storage capacitor electrode. A flowable insulating material is used as a gate insulating layer to planarize the substrate. In the case of the etch stopper type thin film transistor, a photo definable material is used as the etch stopper layer to reduce the parasitic capacitance between the gate electrode and the drain electrode.
1. A liquid crystal display (LCD), comprising:
a first substrate;
a switching element formed on the first substrate;
a passivation layer formed over the first substrate and the switching element and having a substantially flat upper surface;
a black matrix layer formed on the upper surface of the passivation layer;
a spacer formed on the black matrix layer;
a storage electrode formed on the substrate; and
a recess formed in a portion of the passivation layer overlying the storage electrode;
wherein a pixel electrode is formed on the recess.
2. The LCD of claim 1 , wherein the passivation layer is formed of an organic material having a dielectric constant in a range between 2.4 and 3.7.
3. The LCD of claim 1 , further comprising a groove formed on a portion of an upper surface of the passivation layer, wherein the black matrix layer is formed on the groove.
4. The LCD of claim 1 , wherein the switching element comprises:
a gate electrode formed on the substrate;
a gate insulating layer formed on the gate electrode;
a semiconductor layer formed on the gate insulating layer; and
a source electrode and a drain electrode formed on the semiconductor layer,
wherein the pixel electrode is connected to the drain electrode through the passivation layer.
5. The LCD of claim 4 , wherein the semiconductor layer comprises:
an amorphous silicon layer formed on the gate insulating layer; and
an ohmic contact layer formed on the amorphous silicon layer.
6. The LCD of claim 5 , wherein the semiconductor layer further comprises an etch stopper layer formed between the amorphous silicon layer and the ohmic contact layer.
7. The LCD of claim 4 , wherein the gate insulating layer has a substantially flat upper surface.
8. The LCD of claim 1 , wherein the recess is extended from the upper surface of the passivation layer to the gate insulating layer.
9. The LCD of claim 1 , further comprising a conductive pattern formed a portion of the gate insulting layer overlying the storage electrode, wherein the recess is extended from the upper surface of the passivation layer to the conductive pattern.
10. The LCD of claim 1 , further comprising:
a second substrate facing the first substrate; and
a plurality of color filters formed on the second substrate,
wherein the spacer is disposed at a space between two color filters neighboring each other.
11. The LCD of claim 10 , wherein the second substrate further comprises:
a passivation layer formed on the color filters; and
a common electrode formed on the passivation layer.