Vertical nano-size transistor using carbon nanotubes and manufacturing method thereof
The present invention provide a vertical nano-sized transistor using carbon nanotubes capable of achieving high-density integration, that is, tera-bit scale integration, and a manufacturing method thereof, wherein in the vertical nano-sized transistor using carbon nanotubes, holes having diameters of several nanometers are formed in an insulating layer and are spaced at intervals of several nanometers. Carbon nanotubes are vertically aligned in the nano-sized holes by chemical vapor deposition, electrophoresis or mechanical compression to be used as channels. A gate is formed in the vicinity of the carbon nanotubes using an ordinary semiconductor manufacturing method, and then a source and a drain are formed at lower and upper parts of each of the carbon nanotubes thereby fabricating the vertical nano-sized transistor having an electrically switching characteristic.
1. A method of manufacturing a vertical nano-sized transistor using carbon nanotubes, comprising:
(a) forming sources on a semiconductor substrate;
(b) forming an insulating layer using a nonconductor material and forming holes having nano-sized diameters in the insulating layer at portions of the insulating layer corresponding to the sources, where the holes are spaced at intervals of several nanometers;
(c) vertically growing carbon nanotubes on the sources in the holes;
(d) forming gates in the vicinity of the carbon nanotubes;
(e) depositing a nonconductor film over the gates to till the holes; and
(f) forming drains over the nonconductor film and the carbon nanotubes.
2. The method according to claim 1 , wherein while forming the insulating layer, the nonconductor material is one selected from the group consisting of Al 2 O 3 and Si.
3. The method according to claim 1 , wherein vertically growing carbon nanotubes is performed by one method selected from chemical vapor deposition, electrophoresis and mechanical compression.