Methods and devices for synchronizing the timing of logic cards in a packet switching system without data loss
View Patent ↗Synchronous timing techniques provide redundant reference frequencies to enable a packet switching system to continuously generate one or more master clock frequencies when an original reference frequency is lost or unavailable.
1. A synchronous timing circuit comprising:
a first clock circuit for generating a reference frequency based on a first oscillation signal or second oscillation signal, the first circuit comprising a first oscillator for generating the first oscillation signal, a first reference frequency selection section for selecting the first or second oscillation signal and a first delay section for adding a first delay to the first oscillation signal when necessary; and
a second clock circuit for generating substantially the same reference frequency based on the first or second oscillation signal, the second circuit comprising a second oscillator for generating the second oscillation signal, a second reference frequency selection section for selecting the first or second oscillation signal and a second delay section for adding a second delay to the second oscillation signal when necessary.
2. The circuit as in claim 1 wherein the reference frequency comprises 25 MHz.
3. The circuit as in claim 1 further comprising a phase locked loop (PLL) for generating a master clock frequency based on the reference frequency generated by either the first or second clock circuits, and maintaining a fixed relationship between the reference frequency and the master clock frequency.
4. The circuit as in claim 3 wherein the master clock frequency comprises 200 MHz.
5. The circuit as in claim 3 wherein the master clock frequency comprises 25 MHz.
6. The circuit as in claim 1 wherein the circuit comprises a packet switching system.
7. A method for synchronizing the timing of logic cards within a packet switching system comprising:
generating first and second oscillation signals;
detecting whether there has been a failure in the generation of either the first or second oscillation signals;
selecting the first or second oscillation signal which has not failed;
adding a delay to the selected first or second oscillation signal when necessary; and
generating a reference frequency based on the selected first or second oscillation signal.
8. The method as in claim 7 wherein the reference frequency comprises 25 MHz.
9. The method as in claim 7 further comprising:
generating a master clock frequency based on the reference frequency; and
maintaining a fixed relationship between the reference frequency and the master clock frequency.
10. The method as in claim 9 wherein the master clock frequency comprises 200 MHz.
11. The method as in claim 9 wherein the master clock frequency comprises 25 MHz.