Memory macro with modular peripheral circuit elements having a number of line drivers selectable based on number of memory blocks
View Patent ↗A memory macro includes a variable number of memory cell arrays and associated circuits, and peripheral circuit elements such as line drivers, power-source transistors, and power-source capacitors coupled to the associated circuits. Multiple peripheral circuit elements of one type are placed side by side in a certain direction, aligned in that direction with one or more memory cell arrays, and are coupled in parallel to the associated circuits of those memory cell arrays. The number of these peripheral circuit elements is selected according to the number of memory cell arrays aligned with them, so that electrical requirements can be met without unnecessary consumption of space or current.
1. A memory macro having a word line and a first selectable number of memory blocks coupled to said word line, the memory blocks including respective memory cell arrays and associated circuits, the memory macro comprising:
a decoder having an output node; and
a second selectable number of unit word line drivers coupled in parallel to said word line and coupled in parallel to said output node, driving said word line according to a logic level of said output node, the second selectable number of unit word line drivers being equal to the first selectable number of memory blocks.
2. The memory macro of claim 1 , further comprising a metal line electrically interconnecting said second selectable number of unit word line drivers.
3. The memory macro of claim 1 , wherein said unit word line drivers have transistors with gates made of a conductive gate material, further comprising:
an interconnecting line made of said conductive gate material, interconnecting said second selectable number of unit word line drivers.
4. The memory macro of claim 3 , wherein said second selectable number of unit word line drivers are interconnected by extensions of said gates.
5. A memory macro having a column line and a first selectable number of memory blocks coupled to said column line, the memory blocks including respective memory cell arrays and associated sense amplifier arrays, the sense amplifier arrays including sense amplifiers selected by said column line, the memory macro comprising:
a decoder having an output node; and
a second selectable number of unit column line drivers coupled in parallel to said column line and coupled in parallel to said output node, driving said column line according to a logic level of said output node, the second selectable number of unit column line drivers being equal to the first selectable number of memory blocks.
6. The memory macro of claim 5 , further comprising a metal line electrically interconnecting said second selectable number of unit column line drivers.
7. The memory macro of claim 5 , wherein said unit column line drivers have transistors with gates made of a conductive gate material, further comprising:
an interconnecting line made of said conductive gate material, electrically interconnecting said second selectable number of unit word line drivers.
8. The memory macro of claim 7 , wherein said second selectable number of unit column line drivers are interconnected by extensions of said gates.
9. The memory macro of claim 1 , wherein each of said second selectable number of unit word line drivers is sized to provide driving capability for one memory block.
10. The memory macro of claim 5 , wherein each of said second selectable number of unit column line drivers is sized to provide driving capabilities for one memory block.