IP Library Granted Patent US 7,062,241
Granted Patent B2
US 7,062,241 · App. 10/389,611 · Granted Jun 13, 2006

Signal processor and method for the system-independent digital evaluation of mobile communications reception signals of various mobile phone standards

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Quick Facts
Patent No.
US 7,062,241
App. No.
10/389,611
Granted
Jun 13, 2006
Kind
B2
Abstract

Only a single, standard-independent clock rate is generated in a signal processor or a signal processing structure, and correspondingly only precisely one clock frequency generator is then arranged on the chip. The signal processing path includes at least one controllable, asynchronous decimator for transposing the reception signals present in a uniform time frame into a respective standard-specific time frame. This enables signals of a variety of mobile phone standards to be processed.

Claims (19)

1. A signal processor for digitally evaluating mobile communications reception signals compatible with a plurality of different mobile phone standards, comprising:

a single clock frequency generator for processing the reception signals of various mobile phone standards; and

at least one controllable decimator for transposing the reception signals sampled in a uniform time frame into standard-specific time frames;

said decimator having a phase accumulator, a coefficient memory, a buffer memory, a multiplier, and an adder unit;

said coefficient memory having an input, said multiplier having a first input, a second input, and an output;

said phase accumulator having an output connected to said input of said coefficient memory, and said phase accumulator controlling a selection of coefficients with a predefinable control variable;

said buffer memory having an input receiving input data and an output connected to said first input of said multiplier, said coefficient memory having an output connected to said second input of said multiplier, and said adder unit having an input connected to said output of said multiplier and said adder unit adding terms and outputting an addition result.

2. The signal processor according to claim 1 , which further comprises a uniform interface for transferring the reception signals to a variety of assemblies for transposition of a carrier-frequency signal into a low pass position.

3. The signal processor according to claim 2 , wherein said interface contains two analog or digital signals formed of a normal component and a quadrative component or amplitude component and phase component.

4. The signal processor according to claim 1 , wherein said clock frequency generator and said controllable decimator are commonly integrated on a common chip.

5. The signal processor according to claim 1 , wherein said clock frequency generator, said phase accumulator, said coefficient memory, said buffer memory, said multiplier, and said adder unit are commonly integrated on a common chip.

6. A method for digitally evaluating mobile communications reception signals that are compatible with a plurality of different mobile phone standards, which comprises the following method steps: generating a standard-independent clock frequency for signal processing the reception signals;

transposing the reception signals sampled in a uniform time frame into standard-specific time frames with at least one controllable decimator;

providing a decimator with a coefficient memory, a buffer memory, a multiplier, and an adder unit, and controlling the decimator with a phase accumulator, wherein an output of the phase accumulator is connected to an input of the coefficient memory, and controlling a selection of coefficients with the phase accumulator by way of a predefinable control variable;

feeding input data to the buffer memory, outputting from the buffer memory to a first input of the multiplier, outputting from the coefficient memory to a second input of the multiplier, outputting from the multiplier to an input of the adder unit, and adding terms in the adder unit and outputting a result to an output.

7. The method according to claim 6 , which further comprises transferring the reception signals via a uniform interface to assemblies for transposing the carrier-frequency signal into the low pass position.

8. The method according to claim 6 , which comprises processing signals of the mobile phone standards selected from the group consisting of OSM, EDGE, TIA/EIA-136, mixed forms and partial combinations thereof.

9. The method according to claim 6 , which comprises jointly employing circuit components in different signal processing paths for a plurality of mobile phone standards.

10. The method according to claim 6 , which comprises jointly employing circuit components for channel selection, frequency conversion, sampling rate conversion, A/D conversion, noise shaping, and phase and frequency correction in different signal processing paths for a plurality of mobile phone standards.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2022
From: INTEL DEUTSCHLAND GMBH
To: INTEL CORPORATION
Reel/Frame 061356/0001 →
CHANGE OF NAME Recorded Nov 6, 2015
From: INTEL MOBILE COMMUNICATIONS GMBH
To: INTEL DEUTSCHLAND GMBH
Reel/Frame 037057/0061 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2012
From: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
To: INTEL MOBILE COMMUNICATIONS GMBH
Reel/Frame 027556/0709 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2012
From: INFINEON TECHNOLOGIES DELTA GMBH
To: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
Reel/Frame 027531/0108 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE NEEDS TO BE CORRECT TO 09/30/2009 PREVIOUSLY RECORDED ON REEL 026685 FRAME 0688. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 15, 2011
From: INFINEON TECHNOLOGIES AG
To: INFINEON TECHNOLOGIES DELTA GMBH
Reel/Frame 027245/0484 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2011
From: INFINEON TECHNOLOGIES AG
To: INFINEON TECHNOLOGIES DELTA GMBH
Reel/Frame 026685/0688 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE ADDRESS OF: INFINEON TECHNOLOGIES AG, ST.-MARTIN-STRASSE 53, D-81669 MUENCHEN, GERMANY. PREVIOUSLY RECORDED ON REEL 017173 FRAME 0220. ASSIGNOR(S) HEREBY CONFIRMS THE INFINEON TECHNOLOGIES AG, RIDLERSTRASSE 55, D-80339 MUENCHEN, GERMANY IS INCORRECT.. Recorded Mar 1, 2006
From: KRUEGER, MARTIN; WENZEL, DIETMAR
To: INFINEON TECHNOLOGIES AG
Reel/Frame 017233/0256 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2006
From: KRUEGER, MARTIN; WENZEL, DIETMAR
To: INFINEON TECHNOLOGIES AG
Reel/Frame 017173/0220 →