Methods of fabricating a cross-point resistor memory array
Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions. The resistive cross-point memory device is formed by doping lines within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes. Bottom electrodes are then formed over the diodes with a layer of resistive memory material overlying the bottom electrodes. Top electrodes may then be added at an angled to form a cross-point array defined by the lines and the top electrodes.
1. A method of manufacturing a memory structure comprising:
a) providing a semiconductor substrate;
b) forming a plurality of doped lines overlying the substrate;
c) forming a plurality of diodes by forming doped regions of the opposite polarity in contact with regions of the plurality of doped lines;
d) depositing a bottom electrode overlying each doped region;
e) depositing a layer of perovskite material overlying the bottom electrode;
f) removing the layer of perovskite material from regions outside a memory array area, whereby the layer of perovskite material remains within the memory array area; and
g) forming a plurality of top electrodes overlying the layer of perovskite material.
2. The method of claim 1 , wherein the doped lines are doped n-type.
3. The method of claim 2 , wherein the doped regions of the opposite polarity are p-type regions.
4. The method of claim 3 , wherein the doped regions of the opposite polarity are formed by implanting boron ions.
5. The method of claim 4 , wherein the boron ions are implanted at an energy of between approximately 5 keV and 15 keV and a dose of between approximately 1×10 15 /cm 2 and 5×10 15 /cm 2 .
6. The method of claim 3 , wherein the doped regions of the opposite polarity are formed by implanting BF 2 ions.
7. The method of claim 6 , wherein the BF 2 ions are implanted at an energy of between approximately 40 keV and 80 keV and a dose of between approximately 1×10 15 /cm 2 and 5×10 15 /cm 2 .
8. The method of claim 1 , wherein the bottom electrode material is platinum, iridium, or ruthenium.
9. The method of claim 1 , wherein the perovskite material is a colossal magnetoresistance (CMR) material.
10. The method of claim 1 , wherein the perovskite material is Pr 0.7 Ca 0.3 MnO 3 (PCMO).
11. The method of claim 1 , wherein the perovskite material is Gd 0.7 Ca 0.3 BaCo 2 O 5+5 .
12. The method of claim 1 , wherein the top electrodes overly the doped lines forming a cross-point memory configuration.
13. A method of forming a resistive memory array comprising:
a) providing a substrate;
b) depositing a first layer of oxide over the substrate and patterning it to form a plurality of parallel lines;
c) implanting a dopant into the open lines to form doped lines;
d) forming silicon nitride lines perpendicular to the doped lines;
e) depositing a second layer of oxide over the silicon nitride lines;
f) polishing the oxide and silicon nitride down to the level of the first layer of oxide;
g) removing the silicon nitride;
h) forming spacers by depositing a third layer of oxide and then plasma etching to expose select regions of the doped lines;
i) implanting ions into the exposed regions, whereby a diode is formed;
j) depositing bottom electrodes over the exposed regions and polishing the bottom electrodes level with the first oxide layer;
k) depositing a resistive memory material overlying the bottom electrodes; and
l) forming top electrodes overlying the resistive memory material and aligned with the bottom electrodes.
14. The method of claim 13 , further comprising depositing a polysilicon stop overlying the first oxide layer prior to depositing the silicon nitride.
15. The method of claim 13 , wherein the dopant implanted to form the doped lines is an n-type dopant.
16. The method of claim 13 , wherein polishing the second oxide layer and the silicon nitride layer further comprises polishing down to the polysilicon stop and removing the remaining polysilicon stop.
17. The method of claim 13 , further comprising depositing a barrier metal over the exposed regions prior to depositing the bottom electrodes.