Non-contiguous masked refresh for an integrated circuit memory
View Patent ↗A refresh circuit is used for refreshing or masking from refresh non-contiguous subarrays in an integrated circuit memory array. At the initiation of each masked refresh cycle the address inputs, which normally are ignored, are evaluated to indicate which subarrays should be refreshed and which should be not refreshed. Power is saved due to the flexibility in determining which subarrays are refreshed at each new refresh cycle.
1. A circuit for refreshing an integrated circuit memory comprising:
a plurality of output latches;
a plurality of refresh counters;
a plurality of memory subarrays; and
a match circuit for comparing the output of the output latches with current refresh counter data and for generating a refresh match signal for selectively masking the refresh of non-contiguous memory subsarrays.
2. The circuit of claim 1 further comprising means for masking the refresh of different non-contiguous memory arrays on subsequent refresh cycles.
3. The circuit of claim 1 in which the integrated circuit memory comprises a clocked DRAM integrated circuit memory.
4. The circuit of claim 1 in which the integrated circuit memory comprises a synchronous DRAM integrated circuit memory.
5. A method for refreshing an integrated circuit memory comprising a plurality of output latches, plurality of refresh counters, and a plurality of memory subarrays comprising:
comparing the output of the output latches with current refresh counter data;
generating thereafter a refresh match signal; and
using the refresh match signal for selectively masking the refresh of non-contiguous memory subarrays.
6. The method of claim 5 further comprising masking the refresh of different non-contiguous memory arrays on subsequent refresh cycles.
7. The method of claim 5 further comprising refreshing a clocked DRAM integrated circuit memory.
8. The method of claim 5 further comprising refreshing a synchronous DRAM integrated circuit memory.
9. A refresh circuit for an integrated circuit memory comprising:
a plurality of refresh counters;
an increment logic circuit coupled to at least one of the refresh counters;
a plurality of row input latches coupled to the plurality of refresh counters;
a refresh control circuit for receiving control and clock signals coupled to at least one of the refresh counters and to at least one of the row input latches;
a plurality of output latches coupled to the plurality of row input latches; and
a match circuit for comparing the output of the output latches with current refresh counter data and for generating a refresh match signal.
10. The refresh circuit of claim 9 comprising sixteen refresh counters corresponding to sixteen memory subarrays.
11. The refresh circuit of claim 9 comprising sixteen row input latches.
12. The refresh circuit of claim 9 comprising sixteen output latches.
13. The refresh circuit of claim 9 in which at least one of the row input latches comprises a half-cycle latch.
14. The refresh circuit of claim 9 in which at least one of the output latches comprises a half-cycle latch.
15. The refresh circuit of claim 9 further comprising in input latch for receiving control and clock signals coupled to the refresh control circuit.
16. The refresh circuit of claim 15 in which the input latch comprises a full-cycle latch.
17. The refresh circuit of claim 15 in which the input latch further comprises means for generating a control signal.
18. The refresh circuit of claim 15 further comprising a mask circuit coupled to the match circuit and the input latch for generating a refresh mask signal.
19. The refresh circuit of claim 18 further comprising an output circuit coupled to the mask circuit.
20. The refresh circuit of claim 18 further comprising an output circuit for receiving the refresh mask signal, as well as clock and control signals, for generating an inhibit/activate refresh control signal.