Self-adjusting pixel clock and method therefor

1. A pixel clock generating circuit, comprising:

a digital circuit generating a first signal, the first signal corresponding to the relative frequency of the pixel clock as compared with a predetermined desired pixel clock frequency, and

an analog circuit electrically coupled to the digital circuit, the analog circuit comprising:

a reverse biased variable capacitance device having an anode and a cathode;

an integrator having an input coupled to the digital circuit and an output coupled to the cathode of the reverse biased variable capacitor, the integrator arranged to integrate the first signal received from the digital circuit and produce an output voltage across the reverse biased variable capacitance device such that the output voltage causes the capacitance of the reverse biased capacitor to change if the pixel clock is not operating at the predetermined desired pixel clock frequency; and

a comparator circuit electrically coupled to the anode of the reverse biased variable capacitor, the comparator circuit producing the pixel clock having a frequency based on the capacitance of the reverse biased capacitor.

2. The pixel clock generating circuit according to claim 1 , wherein the output voltage causes the capacitance of the reverse biased variable capacitance device to decrease if the pixel clock frequency is slower than the predetermined desired pixel clock frequency and the output voltage causes the capacitance of the reverse biased variable capacitance device to increase if the pixel clock frequency is faster than the predetermined desired pixel clock frequency.

3. The pixel clock generating circuit according to claim 2 , wherein the reverse biased variable capacitance device is a reverse biased variable capacitance diode.

4. The pixel clock generating circuit according to claim 2 , wherein a decrease in the capacitance of the reverse biased variable capacitance device causes an increase in the pixel clock frequency and an increase in the capacitance of the reverse biased variable capacitance device causes a decrease in the pixel clock frequency.

5. The pixel clock generating circuit according to claim 1 , wherein the output voltage across the reverse biased variable capacitance device is based at the least in part on a pulse width of the first signal.

6. The pixel clock generating circuit according to claim 5 , wherein the output voltage across the reverse biased variable capacitance device is further based at least in part on a polarity of the first signal.

7. The pixel clock generating circuit according to claim 1 , wherein the digital circuit includes:

a master clock source;

a first binary counter electrically coupled to the master clock source;

a second binary counter having:

an input electrically coupled to the pixel clock produced by the comparator circuit; and

an output;

a digital comparator electrically coupled to the output of the second binary counter, the comparator being arranged to compare the output of the second binary counter with a predetermined reference count; and

a logic circuit electrically coupled to the digital comparator and the first binary counter, the logic circuit receiving digital signals from the digital comparator and the first binary counter, the logic circuit generating the first signal based on:

a count of the first binary counter; and

a comparison of the count of the second binary counter with the predetermined reference count.

8. The pixel clock generating circuit according to claim 7 , wherein the logic circuit includes an exclusive or (XOR) gate, the XOR gate producing an output signal based on a count signal received from the first binary counter and a signal received from the digital comparator corresponding to a condition in which a count of the second binary counter is greater than the predetermined reference count.

9. The pixel clock generating circuit according to claim 8 , wherein the logic circuit further includes an AND gate, the and gate being electrically coupled to the XOR gate to receive the output signal there from, the AND gate being arranged to produce an output signal based on a comparison of the signal received from the XOR gate with a composite synchronization signal.

10. The pixel clock generating circuit according to claim 9 , wherein the logic circuit further includes a tri-state buffer, the tri-state buffer having:

a signal input arranged to receive a signal from the digital comparator corresponding to a condition in which a count of the second binary counter is less than the predetermined reference count, the XOR gate;

a signal output; and

an enabling input which, when activated, causes a signal present at that signal input to be substantially presented at the signal output, the enabling input being electrically coupled to the AND gate to receive the output signal there from.

11. A method for generating a pixel clock for use in synchronizing the display of characters on a display monitor, the method comprising:

generating a first signal, the first signal corresponding to the relative frequency of the pixel clock as compared with a predetermined desired pixel clock frequency, and

integrating the first signal to produce an output voltage across a reverse biased variable capacitance device such that the output voltage causes the capacitance of the reverse biased capacitor to change if the pixel clock is not operating at the predetermined desired pixel clock frequency; and

generating the pixel clock at a frequency based on the capacitance of the reverse biased capacitor.

12. The method according to claim 11 , further comprising:

decreasing the capacitance of the reverse biased variable capacitance device if the pixel clock frequency is slower than the predetermined desired pixel clock frequency; and

increasing the capacitance of the reverse biased variable capacitance device if the pixel clock frequency is faster than the predetermined desired pixel clock frequency.

13. The method according to claim 12 , further comprising:

increasing the pixel clock frequency if the capacitance of the reverse biased variable capacitance device decreases; and

decreasing the pixel clock frequency if the capacitance of the reverse biased variable capacitance device increases.

14. The method according to claim 13 , further comprising:

providing a master clock source;

electrically coupling a first binary counter to the master clock source;

electrically coupling an input of a second binary counter to the pixel clock;

electrically coupling a digital comparator to an output of the second binary counter;

comparing the output of the second binary counter with a predetermined reference count; and

generating the first signal based on a count of the first binary counter and a comparison of the count of the second binary counter with the predetermined reference count.

15. A video display circuit for overlaying characters with an underlying video signal for display on a display monitor, the video display circuit comprising:

a video controller, the video controller receiving a video input and overlaying character data onto the video input to create a video output;

a random access memory electrically coupled to the video controller, the random access memory storing the overlay character data;

a pixel clock generating circuit providing a clock for synchronizing retrieval of the overlay character data from the random access memory, the pixel clock generating circuit, comprising:

a digital circuit generating a first signal, the first signal corresponding to the relative frequency of the pixel clock as compared with a predetermined desired pixel clock frequency, and

an analog circuit electrically coupled to the digital circuit, the analog circuit comprising:

a reverse biased variable capacitance device having an anode and a cathode;

an integrator having an input coupled to the digital circuit and an output coupled to the cathode of the reverse biased variable capacitor, the integrator arranged to integrate the first signal received from the digital circuit and produce an output voltage across the reverse biased variable capacitance device such that the output voltage causes the capacitance of the reverse biased capacitor to change if the pixel clock is not operating at the predetermined desired pixel clock frequency; and

a comparator circuit electrically coupled to the anode of the reverse biased variable capacitor, the comparator circuit producing the pixel clock having a frequency based on the capacitance of the reverse biased capacitor.

16. The video display circuit according to claim 15 , wherein the output voltage causes the capacitance of the reverse biased variable capacitance device to decrease if the pixel clock frequency is slower than the predetermined desired pixel clock frequency and the output voltage causes the capacitance of the reverse biased variable capacitance device to increase if the pixel clock frequency is faster than the predetermined desired pixel clock frequency.

17. The video display circuit according to claim 16 , wherein the reverse biased variable capacitance device is a reverse biased variable capacitance diode.

18. The video display circuit according to claim 16 , wherein a decrease in the capacitance of the reverse biased variable capacitance device causes an increase in the pixel clock frequency and an increase in the capacitance of the reverse biased variable capacitance device causes a decrease in the pixel clock frequency.

19. The video display circuit according to claim 15 , wherein the output voltage across the reverse biased variable capacitance device is based at least in part on a pulse width of the first signal.

20. The video display circuit according to claim 19 , wherein the output voltage across the reverse biased variable capacitance device is further based at least in part on a polarity of the first signal.

21. The video display circuit according to claim 15 , wherein the digital circuit includes:

a master clock source;

a first binary counter electrically coupled to the master clock source;

a second binary counter having:

an input electrically coupled to the pixel clock produced by the comparator circuit; and

an output;

a digital comparator electrically coupled to the output of the second binary counter, the comparator being arranged to compare the output of the second binary counter with a predetermined reference count; and

a logic circuit electrically coupled to the digital comparator and the first binary counter, the logic circuit receiving digital signals from the digital comparator and the first binary counter, the logic circuit generating the first signal based on:

a count of the first binary counter; and

a comparison of the count of the second binary counter with the predetermined reference count.

22. The video display circuit according to claim 21 , wherein the logic circuit includes an exclusive or (XOR) gate, the XOR gate producing an output signal based on a count signal received from the first binary counter and a signal received from the digital comparator corresponding to a condition in which a count of the second binary counter is greater than the predetermined reference count.

23. The video display circuit according to claim 22 , wherein the logic circuit further includes an AND gate, the and gate being electrically coupled to the XOR gate to receive the output signal there from, the AND gate being arranged to produce an output signal based on a comparison of the signal received from the XOR gate with a composite synchronization signal.

24. The video display circuit according to claim 23 , wherein the logic circuit further includes a tri-state buffer, the tri-state buffer having:

a signal input arranged to receive a signal from the digital comparator corresponding to a condition in which a count of the second binary counter is less than the predetermined reference count, the XOR gate;

a signal output; and

an enabling input which, when activated, causes a signal present at that signal input to be substantially presented at the signal output, the enabling input being electrically coupled to the AND gate to receive the output signal there from.