On-chip clock generator allowing rapid changes of on-chip clock frequency

1. A method comprising:

sending an output of a free-running counter to a comparator for a clock shaper logic unit, the free-running counter incremented every time a double-speed clock rises for an on-chip system;

sending at least one input from a central processing unit (CPU) to the comparator for the clock shaper logic unit, the at least one input specifying a desired frequency; and

producing a central processing unit (CPU) clock in the clock shaper logic unit based on the output of the free-running counter and the at least one input specifying the desired frequency by comparing a bit-reversed version of the output of the free-running counter with the at least one input specifying the desired frequency.

2. The method of claim 1 , wherein producing the central processing unit (CPU) clock in the clock shaper logic unit based on comparing the bit-reversed version of the output of the free-running counter with the at least one input specifying the desired frequency further comprises adjusting the desired frequency at any time.

3. The method of claim 2 , wherein producing the central processing unit (CPU) clock in the clock shaper logic unit based on comparing the bit-reversed version of the output of the free-running counter with the at least one input specifying the desired frequency further comprises determining the central processing unit (CPU) clock using an output of a clock flop having an input inverted only if the bit-reversed version of the output of the free-running counter one input specifying the desired frequency.

4. The method of claim 1 , wherein producing the central processing unit (CPU) clock in the clock shaper logic unit based on comparing the bit-reversed version of the output of the free-running counter with the at least one input specifying the desired frequency further comprises adjusting the desired frequency in at least one of hardware and software based on a measurement of an amount of work the central processing unit (CPU) is asked to perform.

5. The method of claim 4 , wherein producing the central processing unit (CPU) clock in the clock shaper logic unit based on comparing the bit-reversed version of the output of the free-running counter with the at least one input specifying the desired frequency further comprises determining the central processing unit (CPU) clock using an output of a clock flop having an input inverted only if the bit-reversed version of the output of the free-running counter is not greater than the at least one input specifying the desired frequency.

6. The method of claim 1 , wherein producing the central processing unit (CPU) clock in the clock shaper logic unit based on comparing the bit-reversed version of the output of the free-running counter with the at least one input specifying the desired frequency further comprises adjusting the desired frequency when a specified condition occurs.

7. The method of claim 6 , wherein producing the central processing unit (CPU) clock in the clock shaper logic unit based on comparing the bit-reversed version of the output of the free-running counter with the at least one input specifying the desired frequency further comprises determining the central processing unit (CPU) clock using an output of a clock flop having an input inverted only if the bit-reversed version of the output of the free-running counter is not greater than the at least one input specifying the desired frequency.

8. The method of claim 1 , wherein producing the central processing unit (CPU) clock in the clock shaper logic unit based on comparing the bit-reversed version of the output of the free-running counter with the at least one input specifying the desired frequency further comprises allowing the central processing unit (CPU) clock to linger at a faster speed to finish processing in the central processing unit (CPU) and to go back to a slower speed thereafter.

9. The method of claim 8 , wherein producing the central processing unit (CPU) clock in the clock shaper logic unit based on comparing the bit-reversed version of the output of the free-running counter with the at least one input specifying the desired frequency further comprises determining the central processing unit (CPU) clock using an output of a clock flop having an input inverted only if the bit-reversed version of the output of the free-running counter is not greater than the at least one input specifying the desired frequency.

10. The method of claim 1 , wherein producing the central processing unit (CPU) clock in the clock shaper logic unit based on comparing the bit-reversed version of the output of the free-running counter with the at least one input specifying the desired frequency further comprises determining the central processing unit (CPU) clock using an output of a clock flop having an input inverted only if the bit-reversed version of the output of the free-running counter is not greater than the at least one input specifying the desired frequency.

11. The method of claim 1 , wherein producing the central processing unit (CPU) clock in the clock shaper logic unit based on comparing the bit-reversed version of the output of the free-running counter with the at least one input specifying the desired frequency further comprises determining the central processing unit (CPU) clock using an output of a clock flop having an input up-righted if the bit-reversed version of the output of the free-running counter is less than the at least one input specifying the desired frequency.

12. The method of claim 1 , wherein the method is performed by instructions encoded within a computer-readable, program storage device and wherein when executed by a computer the instructions perform the method.

13. The method of claim 1 , wherein the method is performed by a computer that has been programmed to perform the method.

14. The method of claim 1 , wherein the method is performed within an on-chip system.

15. An apparatus comprising:

a clock shaper logic unit having a comparator;

a free-running counter capable of sending an output to the comparator of the clock shaper logic unit, the free-running counter incremented every time a double-speed clock rises for the on-chip system; and

a central processing unit (CPU) capable of sending at least one input to the comparator of the clock shaper logic unit, the at least one input specifying a desired frequency, wherein the clock shaper logic unit is capable of producing a central processing unit (CPU) clock based on the output of the free-running counter and the at least one input specifying the desired frequency by comparing a bit-reversed version of the output of the free-running counter with the at least one input specifying the desired frequency.

16. The apparatus of claim 15 , wherein the clock shaper logic unit is capable of adjusting the desired frequency at any time.

17. The apparatus of claim 16 , wherein the clock shaper logic unit is capable of determining the central processing unit (CPU) clock using an output of a clock flop having an input inverted only if the bit-reversed version of the output of the free-running counter is not greater than the at least one input specifying the desired frequency.

18. The apparatus of claim 15 , wherein the clock shaper logic unit is capable of adjusting the desired frequency in at least one of hardware and software based on a measurement of an amount of work the central processing unit (CPU) is asked to perform.

19. The apparatus of claim 18 , wherein the clock shaper logic unit is capable of determining the central processing unit (CPU) clock using an output of a clock flop having an input inverted only if the bit-reversed version of the output of the free-running counter is not greater than the at least one input specifying the desired frequency.

20. The apparatus of claim 15 , wherein the clock shaper logic unit is capable of adjusting the desired frequency when a specified condition occurs.

21. The apparatus of claim 20 , wherein the clock shaper logic unit is capable of determining the central processing unit (CPU) clock using an output of a clock flop having an input inverted only if the bit-reversed version of the output of the free-running counter is not greater than the at least one input specifying the desired frequency.

22. The apparatus of claim 15 , wherein the clock shaper logic unit is capable of allowing the central processing unit (CPU) clock to linger at a faster speed to finish processing in the central processing unit (CPU) and to go back to a slower speed thereafter.

23. The apparatus of claim 22 , wherein the clock shaper logic unit is capable of determining the central processing unit (CPU) clock using an output of a clock flop having an input inverted only if the bit-reversed version of the output of the free-running counter is not greater than the at least one input specifying the desired frequency.

24. The apparatus of claim 15 , wherein the clock shaper logic unit is capable of determining the central processing unit (CPU) clock using an output of a clock flop having an input inverted only if the bit-reversed version of the output of the free-running counter is not greater than the at least one input specifying the desired frequency.

25. The apparatus of claim 15 , wherein the clock shaper logic unit, the free-running counter capable of sending, and the CPU are all located within an on-chip system.

26. The apparatus of claim 15 , wherein the central processing unit (CPU) clock may be encoded as an n-bit number and wherein desired frequency may specify one of 2 n discrete flip-flop rates.

27. An apparatus comprising:

means for sending an output of a free-running counter to a comparator for a clock shaper logic unit, the free-running counter incremented every time a double-speed clock rises for an on-chip system;

means for sending at least one input from a central processing unit (CPU) to the comparator for the clock shaper logic unit, the at least one input specifying a desired frequency; and

means for producing a central processing unit (CPU) clock in the clock shaper logic unit based on the output of the free-running counter and the at least one input specifying the desired frequency by comparing a bit-reversed version of the output of the free-running counter with the at least one input specifying the desired frequency.

28. The apparatus of claim 27 , wherein the means for producing the central processing unit (CPU) clock in the clock shaper logic unit based on comparing the bit-reversed version of the output of the free-running counter with the at least one input specifying the desired frequency further comprises means for adjusting the desired frequency at any time.

29. The apparatus of claim 28 , wherein the means for producing the central processing unit (CPU) clock in the clock shaper logic unit based on comparing the bit-reversed version of the output of the free-running counter with the at least one input specifying the desired frequency further comprises means for determining the central processing unit (CPU) clock using an output of a clock flop having an input inverted only if the bit-reversed version of the output of the free-running counter is not greater than the at least one input specifying the desired frequency.

30. The apparatus of claim 27 , wherein the means for producing the central processing unit (CPU) clock in the clock shaper logic unit based on comparing the bit-reversed version of the output of the free-running counter with the at least one input specifying the desired frequency further comprises means for adjusting the desired frequency in at least one of hardware and software based on a measurement of an amount of work the central processing unit (CPU) is asked to perform.

31. The apparatus of claim 30 , wherein the means for producing the central processing unit (CPU) clock in the clock shaper logic unit based on comparing the bit-reversed version of the output of the free-running counter with the at least one input specifying the desired frequency further comprises means for determining the central processing unit (CPU) clock using an output of a clock flop having an input inverted only if the bit-reversed version of the output of the free-running counter is not greater than the at least one input specifying the desired frequency.

32. The apparatus of claim 27 , wherein the means for producing the central processing unit (CPU) clock in the clock shaper logic unit based on comparing the bit-reversed version of the output of the free-running counter with the at least one input specifying the desired frequency further comprises means for adjusting the desired frequency when a specified condition occurs.

33. The apparatus of claim 32 , wherein the means for producing the central processing unit (CPU) clock in the clock shaper logic unit based on comparing the bit-reversed version of the output of the free-running counter with the at least one input specifying the desired frequency further comprises means for determining the central processing unit (CPU) clock using an output of a clock flop having an input inverted only if the bit-reversed version of the output of the free-running counter is not greater than the at least one input specifying the desired frequency.

34. The apparatus of claim 27 , wherein the means for producing the central processing unit (CPU) clock in the clock shaper logic unit based on comparing the bit-reversed version of the output of the free-running counter with the at least one input specifying the desired frequency further comprises means for allowing the central processing unit (CPU) clock to linger at a faster speed to finish processing in the central processing unit (CPU) and to go back to a slower speed thereafter.

35. The apparatus of claim 34 , wherein the means for producing the central processing unit (CPU) clock in the clock shaper logic unit based on comparing the bit-reversed version of the output of the free-running counter with the at least one input specifying the desired frequency further comprises means for determining the central processing unit (CPU) clock using an output of a clock flop having an input inverted only if the bit-reversed version of the output of the free-running counter is not greater than the at least one input specifying the desired frequency.

36. The apparatus of claim 27 , wherein the means for producing the central processing unit (CPU) clock in the clock shaper logic unit based on comparing the bit-reversed version of the output of the free-running counter with the at least one input specifying the desired frequency further comprises means for determining the central processing unit (CPU) clock using an output of a clock flop having an input inverted only if the bit-reversed version of the output of the free-running counter is not greater than the at least one input specifying the desired frequency.