System-on-a-chip having an on-chip processor and an on-chip dynamic random access memory (DRAM)

1. A system-on-a-chip device consisting of:

an on-chip processor;

an on-chip dynamic random access memory (DRAM) capable of communicating with the on-chip processor;

an on-chip peripheral component interconnect (PCI) input/output (I/O) bus capable of communicating with the on-chip processor and the on-chip dynamic random access memory (DRAM);

an on-chip arbiter capable of communicating with the component interconnect (PCI) input/output (I/O) bus;

an on-chip expansion bus (E-bus) input/output (I/O) bus;

an on-chip expansion bus (E-bus) controller capable of communicating with the on-chip expansion bus (E-bus) input/output (I/O) bus;

an on-chip Ethernet controller;

an on-chip universal serial bus Host controller;

an on-chip universal asynchronous receiver/transmitter (UART) capable of communicating with the on-chip expansion bus (E-bus) input/output (I/O) bus;

an on-chip Smart Card Interface (SCI) universal asynchronous receiver/transmitter (UART) capable of communicating with the on-chip expansion bus (E-bus) input/output (I/O) bus;

an on-chip I 2 C universal asynchronous receiver/transmitter (UART) capable of communicating with the on-chip expansion bus (E-bus) input/output (I/O) bus;

an on-chip GPIO capable of communicating with the on-chip expansion bus (E-bus) input/output (I/O) bus;

an on-chip joint test access group (JTAG) device;

an on-chip AC97 interface capable of communicating with the on-chip expansion bus (E-bus) input/output (I/O) bus;

an on-chip private flash bus capable of latching configuration options at power-up;

a first on-chip peripheral component interconnect (PCI) controller capable of communicating with the on-chip peripheral component interconnect (PCI) input/output (I/O) bus, the on-chip memory controller, the on-chip processor, and the on-chip dynamic random access memory (DRAM);

a second on-chip peripheral component interconnect (PCI) controller capable of communicating with the on-chip peripheral component interconnect (PCI) input/output (I/O) bus, the on-chip E-bus controller, the on-chip Ethernet controller, and the on-chip USB Host controller;

a first on-chip phase-lock loop (PLL) clock generator capable of sending a signal to the on-chip processor; an

a second on-chip phase-lock loop(PLL) clock generator capable of sending a signal to the at least one on-chip peripheral component interconnect (PCI) controller.

2. A system-on-a-chip device consisting of:

an on-chip processor consisting of a central processing unit core consisting of one of a V8 or V9 architecture capable of executing a respective V8 or V9 Sparc instruction set, the architecture having a central processing unit clock;

an on-chip dynamic random access memory capable of communicating with the on-chip processor;

at least one on-chip input/output bus capable of communicating with the on-chip processor and the on-chip dynamic random access memory, the on-chip input/output bus consisting of a peripheral component interconnect bus;

an on-chip memory controller capable of communicating with the on-chip processor, the on-chip dynamic random access memory, and the at least one on-chip input/output bus;

an on-chip peripheral component interconnect capable of communicating with the peripheral component interconnect bus, the on-chip peripheral component interconnect having an on-chip peripheral component interconnect clock;

an on-chip peripheral component interconnect controller capable of communicating on-chip and off-chip, the on-chip peripheral component interconnect controller being capable of communicating with the on-chip memory controller and the at least one on-chip input/output bus and with the on-chip dynamic random access memory via the on-chip memory controller;

an on-chip interrupt controller capable of communicating with the on-chip processor;

an on-chip arbiter capable of communicating with the on-chip input/output bus;

a microSPARC IIep device consisting of the on-chip processor, the on-chip dynamic random access memory, the on-chip memory controller, the on-chip peripheral component interconnect controller, the on-chip interrupt controller, and the on-chip arbiter;

a first on-chip phase-lock loop clock generator capable of sending a signal to the central processing unit clock of the on-chip processor;

a second on-chip phase-lock loop clock generator capable of sending a signal to the on-chip peripheral component interconnect controller to the on-chip peripheral component interconnect clock;

an on-chip expansion bus input/output bus;

an on-chip expansion bus input/output bus controller capable of communicating with the on-chip expansion bus input/output bus;

an on-chip Ethernet controller;

an on-chip universal serial bus Host controller;

an on-chip external controller device consisting of the on-chip expansion bus input/output bus controller, the on-chip Ethernet controller, and the on-chip universal serial bus Host controller;

an on-chip peripheral component controller capable of communicating with the on-chip external controller device and the on-chip peripheral component interconnect bus;

an on-chip input/output core consisting of the on-chip peripheral component controller and the on-chip external controller device;

an on-chip Joint Test Access group device;

an on-chip audio bus interface capable of communicating with the on-chip expansion bus input/output bus, the on-chip audio bus interface consisting of an Intel AC97;

an on-chip multi-master bus consisting of an Intel-IV universal asynchronous receiver/transmitter capable of communicating with the on-chip expansion bus input/output bus;

an on-chip Smart Card Interface universal asynchronous receiver/transmitter capable of communicating with the on-chip expansion bus input/output bus;

an on-chip general purpose input/output interface capable of communicating with the on-chip expansion bus input/output bus;

an on-chip universal asynchronous receiver/transmitter capable of communicating with the on-chip expansion bus input/output bus; and

an on-chip private flash bus capable of latching configurations at power up.