Method and apparatus for signal electromigration analysis
View Patent ↗The present application describes various embodiments of a method and an apparatus for determining electromigration risks for signal nets in integrated circuits. A model for each one of the global nets connecting various circuit blocks in an integrated circuit is created using circuit blocks' timing model and detailed standard parasitic format representation (DSPF) of each global net. The final layout of the integrated circuit is not necessary to determine the electromigration risks. The models can be generated during the early stages of the design cycle once the DSPF of the global nets is available.
1. A method for use in a design of an integrated circuit, the method comprising:
prior to preparation of a layout of the integrated circuit design, determining detailed parasitic formats of nets in the integrated circuit design;
substituting, in the integrated circuit design, interface elements coupled at ends of the nets with corresponding driving devices having substantially similar characteristics as the interface elements;
performing electromigration analysis on the nets;
wherein the interface elements represent one or more of an output interface and input interface of respective circuit blocks that include the interface elements in the integrated circuit design;
wherein determining the detailed parasitic formats of the nets comprises:
generating a timing model for each one of the circuit blocks in the integrated circuit;
determining current drive of output interfaces of each circuit block; and
determining input capacitance of input interfaces of each circuit block.
2. The method of claim 1 , wherein the detailed parasitic format represents physical characteristics of the nets.
3. The method of claim 2 , wherein the physical characteristics include one or more of a resistance, a capacitance, impedance and a metal type.
4. The method of claim 1 , wherein the characteristics of the interface elements include one or more of current drive and input capacitance.
5. The method of claim 1 , wherein the driving devices include one or more of an inverter and a buffer.
6. The method of claim 1 , wherein the nets are global signal nets.
7. The method of claim 1 , wherein one or more nets include one or more subnets.
8. The method of claim 1 , wherein performing the electromigration analysis comprises:
simulating current flow on the nets using current drive of the driving devices coupled at the ends of respective nets; and
determining whether the current on the nets exceeds respective predetermined current limits for each net.
9. The method of claim 1 , wherein the electromigration analysis is performed on subnets of the nets.
10. A method of processing one or more design files for a semiconductor integrated circuit, the design files encoding representations of a plurality of circuit blocks and signal nets coupling the circuit blocks, the method comprising:
prior to preparation of a layout of the integrated circuit design, determining detailed parasitic formats of signal nets in the integrated circuit design;
substituting, in the integrated circuit design, interface elements coupled at ends of the signal nets with corresponding driving devices having substantially similar characteristics as the interface elements;
performing electromigration analysis on the signal nets;
wherein the interface elements represent one or more of an output interface and input interface of respective circuit blocks that include the interface elements in the integrated circuit design; and
wherein determining the detailed parasitic format of the signal nets comprises:
generating a timing model for each one of the circuit blocks in the integrated circuit;
determining current drive of the output interfaces of each circuit block; and
determining input capacitance of the input interfaces of each circuit block.
11. The method of claim 10 , wherein the detailed parasitic format represents physical characteristics of the signal nets.
12. The method of claim 11 , wherein the physical characteristics include one or more of a resistance, a capacitance, impedance and a metal type.
13. The method of claim 10 , wherein the characteristics of the interface elements include one or more of current drive and input capacitance.
14. The method of claim 10 , wherein the driving devices include one or more of an inverter and a buffer.
15. The method of claim 10 , wherein the signal nets are global signal nets.
16. The method of claim 10 , wherein one or more signal nets include one or more subnets.
17. The method of claim 10 , wherein performing the electromigration analysis comprises:
simulating current flow on the signal nets using current drive of the driving devices coupled at the ends of respective signal nets; and
determining whether the current on the signal nets exceeds respective predetermined current limits for each net.
18. The method of claim 17 , wherein the electromigration analysis is performed on each one of the subnets of the signal nets.
19. A processor comprising:
means for determining detailed parasitic formats of nets in an integrated circuit design;
means for substituting, in the integrated circuit design, interface elements coupled at ends of the nets with corresponding driving devices having substantially similar characteristics as the interface elements;
means for performing electromigration analysis on the nets; and
wherein the means for determining comprises:
means for generating a timing model for each one of a plurality of circuit blocks in the integrated circuit;
means for determining current drive of output interfaces of each circuit block; and
means for determining input capacitance of input interfaces of each circuit block.
20. The processor of claim 19 , further comprising:
means for simulating current flow on the nets using current drive of the driving devices coupled at the ends of respective nets; and
means for determining whether the current on the nets exceeds respective predetermined current limits for each net.