Address conversion apparatus, address conversion method and computer program
View Patent ↗An address output apparatus capable of retaining a pre-extension upper compatibility of software post memory extension and of accessing separated RAM areas by consecutive addresses, without needing to alter CPU architecture. The address output apparatus includes an address conversion circuit 20 that allots to a RAM 30 a basic RAM area and a first area, being one of two area obtained by dividing an extension RAM area, allots to a RAM 50 a second area, being an area other than the first area of the extension RAM area, and converts logical address signals designated by a CPU 10 to physical address signals based on a state of the allotting.
1. An address conversion apparatus that outputs address signals for accessing readable/writable first and second memories, comprising:
an acquisition unit operable to acquire a logical address value; and
an output unit operable to output an address signal for accessing the first memory when the acquired logical address value is included in a first range, to output an address signal for accessing the first memory when the logical address value is included in a second range separated from the first range by an interval, and to output an address signal for accessing the second memory when the logical address value is included within a third range successive to the second range.
2. The address conversion apparatus of claim 1 , wherein
a head address value of the second range is greater than an end address value of the first range.
3. The address conversion apparatus of claim 1 , wherein
the output unit includes a select signal output subunit operable to specify which range the acquired logical address value is included in, by whether high order bits of the logical address value match high order bits common between the head and end addresses of each range, and to output to the first and second memories a select signal showing which of the first and second memories to access in accordance with a specification result; and
an address conversion subunit operable to output to the first and second memories as an address signal, low order bits that exclude the high order bits from the logical address value.
4. The address conversion apparatus of claim 2 , wherein
the output unit includes a select signal output subunit operable to specify which range the acquired logical address value is included in, by whether high order bits of the logical address value match high order bits common between the head and end addresses of each range, and to output to the first and second memories a select signal showing which of the first and second memories to access in accordance with a specification result; and
an address conversion subunit operable to output to the first and second memories as an address signal, low order bits that exclude the high order bits from the logical address value.
5. The address conversion apparatus of claim 1 , further comprising:
a control unit operable to control a validity and invalidity of operations of the output unit depending on whether the second memory is used.
6. The address conversion apparatus of claim 2 , further comprising:
a control unit operable to control a validity and invalidity of operations of the output unit depending on whether the second memory is used.
7. The address conversion apparatus of claim 3 , further comprising:
a control unit operable to control a validity and invalidity of operations of the output unit depending on whether the second memory is used.
8. An address conversion method that outputs address signals for accessing readable/writable first and second memories, comprising:
an acquisition step of acquiring a logical address value; and
an output step of outputting an address signal for accessing the first memory when the acquired logical address value is included in a first range, outputting an address signal for accessing the first memory when the logical address value is included in a second range separated from the first range by an interval, and outputting an address signal for accessing the second memory when the logical address value is included within a third range successive to the second range.
9. A computer program executed by an address conversion apparatus that outputs address signals for accessing readable/writable first and second memories, comprising:
an acquisition step of acquiring a logical address value; and
an output step of outputting an address signal for accessing the first memory when the acquired logical address value is included in a first range, outputting an address signal for accessing the first memory when the logical address value is included in a second range separated from the first range by an interval, and outputting an address signal for accessing the second memory when the logical address value is included within a third range successive to the second range.